Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 71

IC ENCORE XP MCU FLSH 12K 20QFN

Z8F1233QH020SG

Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Datasheets

Specifications of Z8F1233QH020SG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
Table 39. IRQ1 Enable High Bit Register (IRQ1ENH)
Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)
Table 38. IRQ1 Enable and Priority Encoding
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
where x indicates the register bits from 0–7.
IRQ1ENH[x] IRQ1ENL[x] Priority
0
0
1
1
IRQ1 Enable High and Low Bit Registers
PA7ENH PA6CENH PA5ENH
PA7ENL
R/W
R/W
0
0
7
7
Table 38
registers
interrupt request 1 register. Priority is generated by setting bits in each register.
PA7ENH—Port A Bit[7] interrupt request enable high bit
PA6CENH—Port A Bit[7] or comparator interrupt request enable high bit
PAxENH—Port A Bit[x] interrupt request enable high bit
See the interrupt port select register for selection of either Port A or Port D as the interrupt
source.
PA7ENH—Port A Bit[7] interrupt request enable low bit
PA6CENH—Port A Bit[6] or comparator interrupt request enable low bit
PAxENL—Port A Bit[x] interrupt request enable low bit
0
1
0
1
PA6CENL
(Table 39
describes the priority control for IRQ1. The IRQ1 enable high and low bit
R/W
R/W
6
0
6
0
Disabled
Level 1
Level 2
Level 3
and
PA5ENL
R/W
R/W
Table
5
0
5
0
40) form a priority encoded enabling for interrupts in the
Description
Disabled
Low
Nominal
High
PA4ENH
PA4ENL
R/W
R/W
0
0
4
4
FC4H
FC5H
PA3ENH
PA3ENL
R/W
R/W
3
0
3
0
PA2ENH
PA2ENL
R/W
R/W
Z8 Encore!
0
0
2
2
Product Specification
PA1ENH
PA1ENL
R/W
R/W
1
0
1
0
®
Interrupt Controller
F0830 Series
PA0ENH
PA0ENL
R/W
R/W
0
0
0
0
61

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