Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 86

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

PS025111-1207
GATED Mode
In GATED mode, the timer counts only when the timer input signal is in its Active state
(asserted), as determined by the TPOL bit in the timer control register. When the timer
input signal is asserted, counting begins. A timer interrupt is generated when the timer
input signal is deasserted or a timer reload occurs. To determine whether the timer input
signal deassertion generated the interrupt, read the associated GPIO input value and
compare to the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the timer reload high and low byte
registers. The timer input is the system clock. On reaching the reload value, the timer
generates an interrupt, the count value in the timer high and low byte registers is reset to
0001H
the timer output alternate function is enabled, the timer output pin changes state (from low
to high or from high to low) at timer reset.
Follow the steps below for configuring a timer for GATED mode and for initiating the
count:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value. Writing
3. Write to the timer reload high and low byte registers to set the reload value.
4. Enable the timer interrupt and set the timer interrupt priority by writing to the relevant
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the timer control register to enable the timer.
7. Assert the timer input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external timer
input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the timer control register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the timer input signal, captures
the current count value. The capture value is written to the timer PWM high and low byte
–
–
–
these registers only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting always begins at the reset value of
interrupt registers. By default, the timer interrupt is generated for both input
deassertion and Reload events. You can configure the timer interrupt to be generated
only at the input deassertion event or the Reload event by setting TICONFIG field of
the TxCTL1 register.
and counting resumes (assuming the timer input signal remains asserted). Also, if
Disable the timer
Configure the timer for GATED mode.
Set the prescale value.
Z8 Encore!
0001H
Product Specification
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®
F0830 Series
Timers
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