Z8F0213HH005EG Zilog, Z8F0213HH005EG Datasheet - Page 69

• Manufacturer Part Number: Z8F0213HH005EG
• Description: IC ENCORE MCU FLASH 2K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4044; Z8F0213HH005EG

Table 35. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Interrupt Request 1 Register
Interrupt Request 2 Register
PA7VI
R/W
7
0
The Interrupt Request 1 (IRQ1) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 register to determine if any interrupt requests are pending.
PA7VI—Port A7 Interrupt Request
0 = No interrupt request is pending for GPIO Port A
1 = An interrupt request from GPIO Port A
PA6CI—Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator
1 = An interrupt request from GPIO Port A or Comparator
PAxI—Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x
1 = An interrupt request from GPIO Port A pin x is awaiting service
where x indicates the specific GPIO Port pin number (0–5)
The Interrupt Request 2 (IRQ2) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 register to determine if any interrupt requests are pending.
PA6CI
R/W
6
0
PA5I
R/W
5
0
PA4I
R/W
4
0
FC3H
(Table
(Table
PA3I
R/W
35) stores interrupt requests for both
36) stores interrupt requests for both
3
0
Z8 Encore! XP
PA2I
R/W
2
0
Product Specification
PA1I
R/W
1
0
®
Interrupt Controller
F0823 Series
PA0I
R/W
0
0
59