Z8F0213HH005EG Zilog, Z8F0213HH005EG Datasheet - Page 84

• Manufacturer Part Number: Z8F0213HH005EG
• Description: IC ENCORE MCU FLASH 2K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4044; Z8F0213HH005EG

PS024314-0308
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control register to set the PWM dead band delay value. The
5. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
7. Configure the associated GPIO port pin for the Timer Output and Timer Output
8. Write to the Timer Control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than
registers, the ONE-SHOT mode equation determines the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte Registers. The timer input is the system clock. The
Timer Control register determines if the Capture occurs on a rising edge or a falling edge
–
(typically
reset in PWM mode, counting always begins at the reset value of
deadband delay must be less than the duration of the positive phase of the PWM signal
(as defined by the PWM high and low byte registers). It must also be less than the
duration of the negative phase of the PWM signal (as defined by the difference
between the PWM registers and the Timer Reload registers).
period). The Reload value must be greater than the PWM value.
to the relevant interrupt registers.
Complement alternate functions. The Timer Output Complement function is shared
with the Timer Input function for both timers. Setting the timer mode to Dual PWM
automatically switches the function from Timer In to Timer Out Complement.
PWM Period (s)
PWM Output High Time Ratio (%)
PWM Output High Time Ratio (%)
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
0001H
). This only affects the first pass in PWM mode. After the first timer
=
----------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value Prescale
0001H
×
=
=
is loaded into the Timer High and Low Byte
----------------------------------- - 100
Reload Value
Reload Value PWM Value
------------------------------------------------------------------ -
PWM Value
Reload Value
Z8 Encore! XP
×
–
Product Specification
0001H
TPOL
®
×
F0823 Series
100
.
bit in the
Timers
74