ST72F324BK4T6 STMicroelectronics, ST72F324BK4T6 Datasheet - Page 34
ST72F324BK4T6
Manufacturer Part Number
ST72F324BK4T6
Description
IC MCU 8BIT 16K FLASH 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F324BJ2T6.pdf
(198 pages)
Specifications of ST72F324BK4T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-5594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324BK4T6
Manufacturer:
STM
Quantity:
1 422
Company:
Part Number:
ST72F324BK4T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
ST72F324BK4T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Supply, reset and clock management
6.4
Caution:
6.4.1
34/198
Reset sequence manager (RSM)
The reset sequence manager includes three reset sources as shown in
●
●
●
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of three phases as shown in
●
●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is two clock cycles.
Figure 11. Reset sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See the
section for more details.
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.
External reset source pulse
Internal LVD reset
Internal Watchdog reset
Active Phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
Reset vector fetch
ACTIVE PHASE
Doc ID13466 Rev 4
Figure
256 or 4096 CLOCK CYCLES
13). This detection is asynchronous and therefore the
INTERNAL RESET
RESET
Figure
Electrical characteristics
VECTOR
11:
Figure
FETCH
ST72324B-Auto
ON
weak pull-up
12:
h(RSTL)in