MC68HC908QY1VDTE Freescale Semiconductor, MC68HC908QY1VDTE Datasheet - Page 36
Manufacturer Part Number
IC MCU 1.5K FLASH 16-TSSOP
Specifications of MC68HC908QY1VDTE
LVD, POR, PWM
Number Of I /o
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
-40°C ~ 105°C
Package / Case
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 105 C
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
This program sequence is repeated throughout the memory until all data is programmed.
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, V
allows entry from reset into the monitor mode.
10. Clear the PGM bit
11. Wait for time, t
12. Clear the HVEN bit.
13. After time, t
2. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
8. Wait for time, t
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
PGM bit, must not exceed the maximum programming time, t
2.6.6 FLASH Block Protect
The COP register at location $FFFF should not be written between
steps 5–12, when the HVEN bit is set. Since this register is located at a
valid FLASH address, unpredictable behavior may occur if this location is
written while HVEN is set.
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
(typical 1 μs), the memory can be accessed in read mode again.
(minimum 5 μs).
(minimum 30 μs).
MC68HC908QY/QT Family Data Sheet, Rev. 6
Register. Once the FLBPR is programmed with a value other than
, present on the IRQ pin. This voltage also