C8051F804-GS Silicon Laboratories Inc, C8051F804-GS Datasheet
C8051F804-GS
Specifications of C8051F804-GS
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C8051F804-GS Summary of contents
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Capacitance to Digital Converter - Supports buttons, sliders, wheels, and capacitive proximity sensing - Fast 40 µs per channel conversion time - 16-bit resolution - input channels - Auto-scan and wake-on-touch - Auto-accumulate 4x, 8x, 16, 32x, ...
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C8051F80x-83x 2 Rev. 1.0 ...
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Table of Contents 1. System Overview ..................................................................................................... 15 2. Ordering Information ............................................................................................... 25 3. Pin Definitions.......................................................................................................... 28 4. QFN-20 Package Specifications ............................................................................. 33 5. QSOP-24 Package Specifications .......................................................................... 35 6. SOIC-16 Package Specifications ............................................................................ 37 7. Electrical Characteristics ........................................................................................ 39 ...
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C8051F80x-83x 15.2. Data Memory ................................................................................................... 93 15.2.1. Internal RAM ........................................................................................... 93 15.2.1.1. General Purpose Registers ............................................................ 94 15.2.1.2. Bit Addressable Locations .............................................................. 94 15.2.1.3. Stack ............................................................................................ 94 16. In-System Device Identification............................................................................ 95 17. Special Function Registers................................................................................... 97 18. Interrupts .............................................................................................................. ...
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Port I/O Modes of Operation.......................................................................... 139 23.1.1. Port Pins Configured for Analog I/O...................................................... 139 23.1.2. Port Pins Configured For Digital I/O...................................................... 139 23.1.3. Interfacing Port I Logic ............................................................ 140 23.2. Assigning Port I/O Pins to Analog ...
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C8051F80x-83x 26.4.4. Data Register ........................................................................................ 192 26.5. SMBus Transfer Modes................................................................................. 193 26.5.1. Write Sequence (Master) ...................................................................... 193 26.5.2. Read Sequence (Master) ...................................................................... 194 26.5.3. Write Sequence (Slave) ........................................................................ 195 26.5.4. Read Sequence (Slave) ........................................................................ 196 26.6. SMBus Status Decoding................................................................................ 196 ...
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List of Tables 1. System Overview 2. Ordering Information Table 2.1. Product Selection Guide ......................................................................... 26 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F80x-83x ................................................... 28 4. QFN-20 Package Specifications Table 4.1. QFN-20 Package Dimensions ................................................................ 33 Table ...
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C8051F80x-83x Table 18.1. Interrupt Summary .............................................................................. 104 19. Flash Memory Table 19.1. Flash Security Summary .................................................................... 115 20. Power Management Modes 21. Reset Sources 22. Oscillators and Clock Selection 23. Port Input/Output Table 23.1. Port I/O Assignment for Analog Functions ...
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... Figure 1.2. C8051F801, C8051F807, C8051F813, C8051F819 Block Diagram ..... 17 Figure 1.3. C8051F802, C8051F808, C8051F814, C8051F820 Block Diagram ..... 18 Figure 1.4. C8051F803, C8051F809, C8051F815, C8051F821 Block Diagram ..... 19 Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram ..... 20 Figure 1.6. C8051F805, C8051F811, C8051F817, C8051F823 Block Diagram ..... 21 Figure 1.7. C8051F824, C8051F827, C8051F830, C8051F833 Block Diagram ..... 22 Figure 1 ...
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C8051F80x-83x Figure 13.1. CS0 Block Diagram ............................................................................. 71 Figure 13.2. Auto-Scan Example ............................................................................. 73 Figure 13.3. CS0 Multiplexer Block Diagram ........................................................... 80 14. CIP-51 Microcontroller Figure 14.1. CIP-51 Block Diagram ......................................................................... 82 15. Memory Organization Figure 15.1. C8051F80x-83x Memory Map ...
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Figure 26.3. SMBus Transaction ........................................................................... 182 Figure 26.4. Typical SMBus SCL Generation ........................................................ 184 Figure 26.5. Typical Master Write Sequence ........................................................ 193 Figure 26.6. Typical Master Read Sequence ........................................................ 194 Figure 26.7. Typical Slave Write Sequence .......................................................... 195 Figure 26.8. ...
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C8051F80x-83x List of Registers SFR Definition 8.1. ADC0CF: ADC0 Configuration ...................................................... 50 SFR Definition 8.2. ADC0H: ADC0 Data Word MSB .................................................... 51 SFR Definition 8.3. ADC0L: ADC0 Data Word LSB ...................................................... 51 SFR Definition 8.4. ADC0CN: ADC0 Control ................................................................ 52 ...
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SFR Definition 21.2. RSTSRC: Reset Source ............................................................ 128 SFR Definition 22.1. CLKSEL: Clock Select ............................................................... 130 SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration .............................. 131 SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control ................................... 132 SFR Definition 22.4. OSCXCN: ...
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C8051F80x-83x SFR Definition 28.8. TMR2CN: Timer 2 Control ......................................................... 222 SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 223 SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 223 SFR Definition 28.11. TMR2L: Timer 2 ...
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System Overview C8051F80x-83x devices are fully integrated, mixed-signal, system-on-a-chip capacitive sensing MCUs. Highlighted features are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers. High-speed pipelined 8051-compatible microcontroller core ( MIPS) ...
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C8051F80x-83x CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F800/ ‘F812/ Reset 256 Byte RAM Debug / RST/C2CK Programming 256 Byte XRAM Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator ...
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CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F801/ ‘F813/ Reset 256 Byte RAM Debug / RST/C2CK Programming 256 Byte XRAM Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator External ...
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C8051F80x-83x CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F802/ ‘F814, ‘F820 Reset 256 Byte RAM Debug / RST/C2CK Programming 256 Byte XRAM Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal ...
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CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F803/ ‘F815, ‘F821 Reset 256 Byte RAM Debug / RST/C2CK Programming 256 Byte XRAM Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator ...
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... Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator External XTAL1 Clock XTAL2 Circuit System Clock Configuration Figure 1.5. C8051F804, C8051F810, C8051F816, C8051F822 Block Diagram 20 Port I/O Configuration Digital Peripherals UART Port 0 Drivers Timers 0, 1 Timer 2 / Priority RTC Crossbar Decoder PCA/ ...
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CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F805, ‘F811 ‘F817, ‘F823 Reset 256 Byte RAM Debug / RST/C2CK Programming 256 Byte XRAM Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal ...
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C8051F80x-83x CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F824, ‘F827 Reset ‘F830, ‘F833 Debug / 256 Byte RAM RST/C2CK Programming Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator External ...
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CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F825, ‘F828 Reset ‘F831, ‘F834 Debug / 256 Byte RAM RST/C2CK Programming Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator External XTAL1 ...
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C8051F80x-83x CIP-51 8051 Controller Core Power On Reset Flash Memory ‘F826, ‘F829 Reset ‘F832, ‘F835 Debug / 256 Byte RAM RST/C2CK Programming Hardware P2.0/C2D Peripheral Power Core Power VDD Regulator GND SYSCLK Precision Internal Oscillator External ...
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Ordering Information All C8051F80x-83x devices have the following features: 25 MIPS (Peak) Calibrated Internal Oscillator SMBus/I2C Enhanced SPI UART Programmable counter array (3 channels) 3 Timers (16-bit) 1 Comparator Pb-Free ...
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... C8051F80x-83x Table 2.1. Product Selection Guide C8051F800-GU 17 C8051F801-GU 17 C8051F802-GU 17 C8051F800-GM 17 C8051F801-GM 17 C8051F802-GM 17 C8051F803-GS 13 C8051F804-GS 13 C8051F805-GS 13 C8051F806-GU 17 C8051F807-GU 17 C8051F808-GU 17 C8051F806-GM 17 C8051F807-GM 17 C8051F808-GM 17 C8051F809-GS 13 C8051F810-GS 13 C8051F811-GS 13 C8051F812-GU 17 C8051F813-GU 17 C8051F814-GU 17 C8051F812-GM 17 C8051F813-GM 17 C8051F814-GM 17 C8051F815-GS 13 C8051F816-GS 13 C8051F817-GS 13 C8051F818-GU 17 C8051F819-GU 17 C8051F820-GU 17 C8051F818-GM 17 C8051F819-GM 17 C8051F820- 512 ...
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Table 2.1. Product Selection Guide (Continued) C8051F821- C8051F822- C8051F823-GS 13 — C8051F824- C8051F825- C8051F826-GS 13 — C8051F827- C8051F828- C8051F829-GS 13 — C8051F830- C8051F831- C8051F832-GS ...
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C8051F80x-83x 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F80x-83x Name Pin Pin QSOP-24 QFN-20 GND RST C2CK P2. C2D P0. VREF P0 P0.2/ 2 ...
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Table 3.1. Pin Definitions for the C8051F80x-83x (Continued) Name Pin Pin QSOP-24 QFN-20 SOIC-16 P0 P0. CNVSTR P1.5 ...
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C8051F80x-83x P0.0 1 GND 2 VDD 3 4 RST/C2CK P2.0/C2D 5 Figure 3.1. QFN-20 Pinout Diagram (Top View) 30 C8051F80x-GM C8051F81x-GM C8051F82x-GM Top View GND Rev. 1.0 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 ...
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NC 1 P0.2 2 P0.1 3 P0.0 4 GND 5 C8051F80x-GU VDD 6 C8051F81x-GU RST / C2CK C8051F82x-GU 7 P2.0/C2D 8 P1.7 9 P1 Figure 3.2. QSOP-24 Pinout Diagram (Top View) C8051F80x-83x TOP VIEW 24 ...
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C8051F80x-83x P0.2 P0.1 P0.0 GND VDD RST / C2CK P2.0/C2D P1.3 Figure 3.3. SOIC-16 Pinout Diagram (Top View) 32 TOP VIEW C8051F80x-GS 4 C8051F81x-GS C8051F82x-GS 5 C8051F83x- Rev. 1.0 P0.3 16 P0.4 15 P0.5 ...
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QFN-20 Package Specifications Figure 4.1. QFN-20 Package Drawing Table 4.1. QFN-20 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.25 D 4.00 BSC. D2 2.00 2.15 e 0.50 BSC. E 4.00 BSC. E2 ...
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C8051F80x-83x Figure 4.2. QFN-20 Recommended PCB Land Pattern Table 4.2. QFN-20 PCB Land Pattern Dimensions Dimension Min C1 3.70 C2 3.70 E 0.50 X1 0.20 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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QSOP-24 Package Specifications Figure 5.1. QSOP-24 Package Drawing Table 5.1. QSOP-24 Package Dimensions Dimension Min Nom A — — A1 0.10 — b 0.20 — c 0.10 — D 8.65 BSC E 6.00 BSC E1 3.90 BSC e 0.635 ...
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C8051F80x-83x Figure 5.2. QSOP-24 PCB Land Pattern Table 5.2. QSOP-24 PCB Land Pattern Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based ...
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SOIC-16 Package Specifications Figure 6.1. SOIC-16 Package Drawing Table 6.1. SOIC-16 Package Dimensions Dimension Min Nom A — A1 0.10 A2 1.25 b 0.31 c 0.17 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC Notes: ...
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C8051F80x-83x Figure 6.2. SOIC-16 PCB Land Pattern Table 6.2. SOIC-16 PCB Land Pattern Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on ...
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Electrical Characteristics 7.1. Absolute Maximum Specifications Table 7.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on RST or any Port I/O Pin with respect to GND Voltage on V with respect to GND DD Maximum ...
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C8051F80x-83x 7.2. Electrical Characteristics Table 7.2. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Supply Voltage Digital Supply Current with CPU Active (Normal Mode ) ...
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Table 7.3. Port I/O DC Electrical Characteristics V = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters Conditions Output High Voltage I = –3 mA, Port I/O push-pull –10 µA, Port I/O ...
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C8051F80x-83x Table 7.6. Flash Electrical Characteristics Parameter Flash Size (Note 1) C8051F80x and C8051F810/1 C8051F812/3/4/5/6/7/8/9 and C8051F82x C8051F830/1/2/3/4/5 Endurance (Erase/Write) Erase Cycle Time 25 MHz Clock Write Cycle Time 25 MHz Clock Clock Speed during Flash Write/Erase Operations Note: Includes ...
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Table 7.9. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input, ...
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C8051F80x-83x Table 7.10. Power Management Electrical Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Idle Mode Wake-Up Time Suspend Mode Wake-up Time Table 7.11. Temperature Sensor ...
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Table 7.13. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter Response Time: CP0+ – CP0– = 100 mV * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV Response ...
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C8051F80x-83x 8. 10-Bit ADC (ADC0) ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1 500 ksps, 10-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, a gain stage programmable 0.5x, and a programmable window detector. The ADC is ...
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Output Code Formatting The ADC measures the input voltage with reference to GND. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data ...
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C8051F80x-83x 8.3.2. Tracking Modes The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left ...
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Settling Time Requirements A minimum tracking time is required before each conversion to ensure that an accurate conversion is per- formed. This tracking time is determined by any series impedance, including the AMUX0 resistance, the the ADC0 sampling capacitance, ...
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C8051F80x-83x SFR Definition 8.1. ADC0CF: ADC0 Configuration Bit 7 6 AD0SC[4:0] Name Type 1 1 Reset SFR Address = 0xBC Bit Name 7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the ...
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SFR Definition 8.2. ADC0H: ADC0 Data Word MSB Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBE Bit Name 7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 will read 000000b. Bits 1–0 ...
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C8051F80x-83x SFR Definition 8.4. ADC0CN: ADC0 Control Bit 7 6 AD0EN AD0TM AD0INT Name R/W R/W Type 0 0 Reset SFR Address = 0xE8; Bit-Addressable Bit Name 7 AD0EN ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...
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C8051F80x-83x SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte Bit 7 6 Name Type 0 0 Reset SFR Address = 0xC6 Bit Name 7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits. SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low ...
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Window Detector Example Figure 8.4 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned ...
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C8051F80x-83x 8.5. ADC0 Analog Multiplexer ADC0 on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 uses an analog input multiplexer to select the positive input to the ADC. Any of the following may be selected as the positive input: Port 0 or ...
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SFR Definition 8.9. ADC0MX: AMUX0 Channel Select Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xBB Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4:0 AMX0P[4:0] AMUX0 Positive Input Selection. 00000: 00001: ...
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C8051F80x-83x 9. Temperature Sensor An on-chip temperature sensor is included on the C8051F800/1/2/3/4/5, C8051F812/3/4/5/6/7, C8051F824/5/6, and C8051F830/1/2 which can be directly accessed via the ADC multiplexer in single- ended configuration. To use the ADC to measure the temperature sensor, the ...
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Figure 9.2. Temperature Sensor Error with 1-Point Calibration at 0 °C C8051F80x-83x 20.00 40.00 Temperature (degrees C) Rev. 1.0 5.00 4.00 3.00 2.00 1.00 0.00 60.00 ...
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C8051F80x-83x 10. Voltage and Ground Reference Options The voltage reference MUX is configurable to use an externally connected voltage reference, the on-chip voltage reference, or one of two power supply voltages (see Figure 10.1). The ground reference MUX allows the ...
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External Voltage References To use an external voltage reference, REFSL[1:0] should be set to 00. Bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. 10.2. Internal Voltage Reference Options A 1.65 V high-speed ...
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C8051F80x-83x SFR Definition 10.1. REF0CN: Voltage Reference Control Bit 7 6 REFGND Name R R Type 0 0 Reset SFR Address = 0xD1 Bit Name 7:6 Unused Read = 00b; Write = Don’t Care. 5 REFGND Analog Ground Reference. Selects ...
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Voltage Regulator (REG0) C8051F80x-83x devices include an internal voltage regulator (REG0) to regulate the internal core supply to 1.8 V from a V supply of 1 power-saving mode is built into the regulator to help ...
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C8051F80x-83x SFR Definition 11.1. REG0CN: Voltage Regulator Control Bit 7 6 STOPCF Name R/W R/W Type 0 0 Reset SFR Address = 0xC9 Bit Name 7 STOPCF Stop Mode Configuration. This bit configures the regulator’s behavior when the device enters ...
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Comparator0 C8051F80x-83x devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 12.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...
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C8051F80x-83x The Comparator response time may be configured in software via the CPT0MD register (see SFR Defini- tion 12.2). Selecting a longer response time reduces the Comparator supply current. CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis ...
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SFR Definition 12.1. CPT0CN: Comparator0 Control Bit 7 6 CP0EN CP0OUT CP0RIF Name R/W R Type 0 0 Reset SFR Address = 0x9B Bit Name 7 CP0EN Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. 6 CP0OUT Comparator0 Output ...
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C8051F80x-83x SFR Definition 12.2. CPT0MD: Comparator0 Mode Selection Bit 7 6 CP0RIE Name R R Type 0 0 Reset SFR Address = 0x9D Bit Name 7:6 Unused Read = 00b, Write = Don’t Care. 5 CP0RIE Comparator0 Rising-Edge Interrupt Enable. ...
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Comparator Multiplexer C8051F80x-83x devices include an analog input multiplexer to connect Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 12.3). The CMX0P3– CMX0P0 bits select the Comparator0 positive input; ...
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C8051F80x-83x SFR Definition 12.3. CPT0MX: Comparator0 MUX Selection Bit 7 6 CMX0N[3:0] Name R/W Type 1 1 Reset SFR Address = 0x9F Bit Name 7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection. 20-Pin and 24-Pin Devices 0000 P0.1 0001 P0.3 0010 ...
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Capacitive Sense (CS0) The Capacitive Sense subsystem included on the C8051F800/1/3/4/6/7/9, C8051F810/2/3/5/6/8/9, C8051F821/2/4/5/7/8, C8051F830/1/3/4 uses a capacitance-to-digital circuit to determine the capacitance on a port pin. The module can take measurements from different port pins using the module’s analog ...
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C8051F80x-83x 13.1. Configuring Port Pins as Capacitive Sense Inputs In order for a port pin to be measured by CS0, that port pin must be configured as an analog input (see “23. Port Input/Output” ). Configuring the input multiplexer to ...
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SFR Configuration: Enables Capsense0 CS0CN = 0x80 Enables Auto-scan CS0CF = 0x70 as start-of- conversion source Sets P0.2 as Auto- CS0SS = 0x02 scan starting channel Sets P1.5 as Auto- CS0SE = 0x0D scan ending channel Configures P0.3, P0MDIN = ...
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C8051F80x-83x 13.5. CS0 Conversion Accumulator CS0 can be configured to accumulate multiple conversions on an input channel. The number of samples to be accumulated is configured using the CS0ACU2:0 bits (CS0CF2:0). The accumulator can accumulate 16, 32, ...
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SFR Definition 13.1. CS0CN: Capacitive Sense Control Bit 7 6 CS0EN CS0INT Name R/W R Type 0 0 Reset SFR Address = 0xB0; Bit-Addressable Bit Name 7 CS0EN CS0 Enable. 0: CS0 disabled and in low-power mode. 1: CS0 enabled ...
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C8051F80x-83x SFR Definition 13.2. CS0CF: Capacitive Sense Configuration Bit 7 6 CS0CM[2:0] Name R R/W Type 0 0 Reset SFR Address = 0x9E Bit Name 7 Unused Read = 0b; Write = Don’t care 6:4 CS0CM[2:0] CS0 Start of Conversion ...
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SFR Definition 13.3. CS0DH: Capacitive Sense Data High Byte Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xAC Bit Name 7:0 CS0DH CS0 Data High Byte. Stores the high byte of the last completed 16-bit ...
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C8051F80x-83x SFR Definition 13.5. CS0SS: Capacitive Sense Auto-Scan Start Channel Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xB9 Bit Name 7:5 Unused Read = 000b; Write = Don’t care 4:0 CS0SS[4:0] Starting Channel for ...
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SFR Definition 13.7. CS0THH: Capacitive Sense Comparator Threshold High Byte Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0x97 Bit Name 7:0 CS0THH[7:0] CS0 Comparator Threshold High Byte. High byte of the 16-bit value compared ...
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C8051F80x-83x 13.6. Capacitive Sense Multiplexer The input multiplexer can be controlled through two methods. The CS0MX register can be written to through firmware, or the register can be configured automatically using the modules auto-scan functionality (see “13.3. Automatic Scanning” ). ...
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SFR Definition 13.9. CS0MX: Capacitive Sense Mux Channel Select Bit 7 6 CS0UC Name R/W R Type 1 0 Reset SFR Address = 0x9C Bit Name 7 CS0UC CS0 Unconnected. Disconnects CS0 from all port pins, regardless of the selected ...
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C8051F80x-83x 14. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a ...
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With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion time. ...
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C8051F80x-83x Table 14.1. CIP-51 Instruction Set Summary Mnemonic Description Arithmetic Operations ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM to A ADD A, #data Add immediate to ...
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Table 14.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate ...
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C8051F80x-83x Table 14.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL C, /bit OR ...
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Notes on Registers, Operands and Addressing Modes: Rn—Register R0–R7 of the currently selected register bank. @Ri—Data RAM location addressed indirectly through R0 or R1. rel—8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by ...
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C8051F80x-83x 14.2. CIP-51 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should always be written to the value indicated in the SFR description. Future product versions may use these bits ...
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SFR Definition 14.3. SP: Stack Pointer Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name 7:0 SP[7:0] Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is ...
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C8051F80x-83x SFR Definition 14. Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; Bit-Addressable Bit Name 7:0 B[7:0] B Register. This register serves as a second accumulator for certain arithmetic operations ...
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SFR Definition 14.6. PSW: Program Status Word Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name 7 CY Carry Flag. This bit is set when the last arithmetic operation resulted ...
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C8051F80x-83x 15. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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Program Memory The members of the C8051F80x-83x device family contain 16 kB (C8051F80x and C8051F810/1 (C8051F812/3/4/5/6/7/8/9 and C8051F82x (C8051F830/1/2/3/4/5) of re-programmable Flash memory that can be used as non-volatile program or data storage. The ...
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C8051F80x-83x whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. ...
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In-System Device Identification The C8051F80x-83x has SFRs that identify the device family and derivative. These SFRs can be read by firmware at runtime to determine the capabilities of the MCU that is executing code. This allows the same firmware ...
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... Derivative Identification Byte. Shows the C8051F80x-83x derivative being used. 0xD0: C8051F800; 0xD1: C8051F801; 0xD2: C8051F802; 0xD3: C8051F803 0xD4: C8051F804; 0xD5: C8051F805; 0xD6: C8051F806; 0xD7: C8051F807 0xD8: C8051F808; 0xD9: C8051F809; 0xDA: C8051F810; 0xDB: C8051F811 0xDC: C8051F812; 0xDD: C8051F813; 0xDE: C8051F814; 0xDF: C8051F815 0xE0: C8051F816 ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the C8051F80x-83x's resources and peripher- als. The CIP-51 controller core duplicates the SFRs ...
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C8051F80x-83x Table 17.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xE0 ACC 0xBC ADC0CF 0xE8 ADC0CN 0xC4 ADC0GTH 0xC3 ADC0GTL 0xBE ADC0H 0xBD ADC0L 0xC6 ADC0LTH 0xC5 ADC0LTL 0xBB ADC0MX ...
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Table 17.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0x9E CS0 Configuration CS0CF 0x9C CS0 Mux CS0MX 0xBA Auto Scan End Channel CS0SE 0xB9 Auto Scan Start Channel CS0SS ...
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C8051F80x-83x Table 17.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xED P1MAT 0xF2 P1MDIN 0xA5 P1MDOUT 0xD5 P1SKIP 0xA0 P2 0xA6 P2MDOUT 0xD8 PCA0CN 0xFC PCA0CPH0 0xEA PCA0CPH1 0xEC ...
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Table 17.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0x99 UART0 Data Buffer SBUF0 0x98 UART0 Control SCON0 0xD6 SMBus Slave Address mask SMB0ADM 0xD7 SMBus Slave Address SMB0ADR ...
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C8051F80x-83x 18. Interrupts The C8051F80x-83x includes an extended interrupt system supporting a total of 15 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of ...
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MCU Interrupt Sources and Vectors The C8051F80x-83x MCUs support 15 interrupt sources. Software can simulate an interrupt by setting an interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and ...
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C8051F80x-83x Interrupt Source Interrupt Vector Reset 0x0000 External Interrupt 0 0x0003 (INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B Port Match 0x0043 ADC0 0x004B ...
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SFR Definition 18.1. IE: Interrupt Enable Bit ESPI0 Name R/W R/W Type 0 0 Reset SFR Address = 0xA8; Bit-Addressable Bit Name 7 EA Enable All Interrupts. Globally enables/disables all interrupts. It overrides individual interrupt mask settings. ...
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C8051F80x-83x SFR Definition 18.2. IP: Interrupt Priority Bit 7 6 PSPI0 Name R R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Unused Read = 1b, Write = Don't Care. 6 PSPI0 Serial Peripheral Interface (SPI0) ...
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SFR Definition 18.3. EIE1: Extended Interrupt Enable 1 Bit 7 6 Name Reserved Reserved W W Type 0 0 Reset SFR Address = 0xE6 Bit Name 7 Reserved Must write 0. 6 Reserved Reserved. Must write 0. 5 ECP0 Enable ...
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C8051F80x-83x SFR Definition 18.4. EIE2: Extended Interrupt Enable 2 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xE7 Bit Name 7:2 Unused Read = 000000b; Write = don’t care. 1 ECSGRT Enable Capacitive Sense Greater ...
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SFR Definition 18.5. EIP1: Extended Interrupt Priority 1 Bit 7 6 Name Reserved Reserved W W Type 0 0 Reset SFR Address = 0xF3 Bit Name 7:6 Reserved Must write 0. 5 PCP0 Comparator0 (CP0) Interrupt Priority Control. This bit ...
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C8051F80x-83x SFR Definition 18.6. EIP2: Extended Interrupt Priority 2 Bit 7 6 Name Reserved Reserved Reserved R R Type 0 0 Reset SFR Address = 0xF4 Bit Name 7:2 Reserved 1 PSCGRT Capacitive Sense Greater Than Comparator Priority Control. This ...
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INT0 and INT1 External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active ...
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C8051F80x-83x SFR Definition 18.7. IT01CF: INT0/INT1 Configuration Bit 7 6 IN1PL IN1SL[2:0] Name R/W Type 0 0 Reset SFR Address = 0xE4 Bit Name 7 IN1PL INT1 Polarity. 0: INT1 input is active low. 1: INT1 input is active high. ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX write instruction. Once cleared to logic 0, ...
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C8051F80x-83x 8. Restore previous interrupt state. Steps 4–6 must be repeated for each 512-byte page to be erased. Note: Flash security settings may prevent erasure of some Flash pages, such as the reserved area and the page containing the lock ...
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Table 19.1 summarizes the Flash security features of the C8051F80x-83x devices. Table 19.1. Flash Security Summary Action Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or ...
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C8051F80x-83x the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be generated when the firmware attempts to modify the Flash. The following guidelines are recommended for any system that contains routines ...
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Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash. 19.4.3. System Clock 1. If operating from an ...
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C8051F80x-83x SFR Definition 19.1. PSCTL: Program Store R/W Control Bit 7 6 Name R R Type 0 0 Reset SFR Address =0x8F Bit Name 7:2 Unused Read = 000000b, Write = don’t care. 1 PSEE Program Store Erase Enable. Setting ...
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SFR Definition 19.2. FLKEY: Flash Lock and Key Bit 7 6 Name Type 0 0 Reset SFR Address = 0xB7 Bit Name 7:0 FLKEY[7:0] Flash Lock and Key Register. Write: This register provides a lock and key function for Flash ...
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C8051F80x-83x 20. Power Management Modes The C8051F80x-83x devices have three software programmable power management modes: Idle, Stop, and Suspend. Idle mode and Stop mode are part of the standard 8051 architecture, while Suspend mode is an enhanced power-saving mode implemented ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the controller core to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals ...
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C8051F80x-83x SFR Definition 20.1. PCON: Power Control Bit 7 6 Name Type 0 0 Reset SFR Address = 0x87 Bit Name 7:2 GF[5:0] General Purpose Flags 5–0. These are general purpose flags for use under software control. 1 STOP Stop ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their ...
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C8051F80x-83x 21.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
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Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 21.2). When level above V ...
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C8051F80x-83x SFR Definition 21.1. VDM0CN: V Bit 7 6 Name VDMEN VDDSTAT Type R/W R Reset Varies Varies SFR Address = 0xFF Bit Name 7 VDMEN V Monitor Enable. DD This bit turns the V tem resets until it is ...
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Comparator0 Reset Comparator0 can be configured as a reset source by writing the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the ...
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C8051F80x-83x SFR Definition 21.2. RSTSRC: Reset Source Bit 7 6 FERROR C0RSEF Name R R Type 0 Varies Reset SFR Address = 0xEF Bit Name Description 7 Unused Unused. 6 FERROR Flash Error Reset Flag. 5 C0RSEF Comparator0 Reset Enable ...
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Oscillators and Clock Selection C8051F80x-83x devices include a programmable internal high-frequency oscillator and an external oscilla- tor drive circuit. The internal high-frequency oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 22.1. ...
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C8051F80x-83x SFR Definition 22.1. CLKSEL: Clock Select Bit 7 6 Name CLKRDY CLKDIV[2:0] Type R R/W Reset 0 0 SFR Address = 0xA9 Bit Name 7 CLKRDY System Clock Divider Clock Ready Flag. 0: The selected clock divide setting has ...
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Programmable Internal High-Frequency (H-F) Oscillator All C8051F80x-83x devices include a programmable internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR ...
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C8051F80x-83x SFR Definition 22.3. OSCICN: Internal H-F Oscillator Control Bit 7 6 IOSCEN IFRDY SUSPEND Name R/W R Type 1 1 Reset SFR Address = 0xB2 Bit Name 7 IOSCEN Internal H-F Oscillator Enable Bit. 0: Internal H-F Oscillator Disabled. ...
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External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...
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C8051F80x-83x SFR Definition 22.4. OSCXCN: External Oscillator Control Bit 7 6 XTLVLD XOSCMD[2:0] Name R Type 0 0 Reset SFR Address = 0xB1 Bit Name 7 XTLVLD Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator ...
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External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 22.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...
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C8051F80x-83x 32.768 kHz 22pF* * Capacitor values depend on crystal specifications Figure 22.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 22.3.2. External RC Example network is used as an external oscillator source for the MCU, the ...
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External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 22.1, Option 3. The capacitor should be no greater than 100 pF; however for very ...
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C8051F80x-83x 23. Port Input/Output Digital and analog resources are available through 17 I/O pins (24-pin and 20-pin packages I/O pins (16-pin packages). Port pins P0.0–P1.7 can be defined as general-purpose I/O (GPIO) or assigned to one of the ...
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Port I/O Modes of Operation Port pins P0.0–P1.7 use the Port I/O cell shown in Figure 23.2. Each Port I/O cell can be configured by software for analog I/O or digital I/O using the PnMDIN and PnMDOUT registers. Port ...
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C8051F80x-83x 23.1.3. Interfacing Port I Logic All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than VDD and less than 5.25 ...
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Table 23.1. Port I/O Assignment for Analog Functions Analog Function ADC Input Comparator0 Input CS0 Input Voltage Reference (VREF0) Ground Reference (AGND) External Oscillator in Crystal Mode (XTAL1) External Oscillator in RC Crystal Mode (XTAL2) 23.2.2. Assigning Port ...
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C8051F80x-83x Table 23.2. Port I/O Assignment for Digital Functions Digital Function UART0, SPI0, SMBus, Any Port pin available for assignment by the SYSCLK, PCA0 (CEX0-2 Crossbar. This includes P0.0 - P1.7 and ECI), T0, or T1. have their PnSKIP bit ...
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Priority Crossbar Decoder The Priority Crossbar Decoder assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (exclud- ing UART0, ...
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C8051F80x-83x Port Pin Number 0 1 Special Function Signals TX0 RX0 SCK MISO MOSI 2 NSS SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings 1 Pins P0.0-P1.7 are capable of being assigned ...
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Port P0 Pin Number Special Function Signals TX0 RX0 SCK MISO MOSI 2 NSS SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings P0SKIP In ...
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C8051F80x-83x Port Pin Number 0 Special Function Signals TX0 RX0 SCK MISO MOSI 2 NSS SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Pin Skip Settings In this example, the crossbar is configured to assign the ...
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Port I/O Initialization Port I/O initialization consists of the following steps: 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). If the pin is in analog mode, a ‘1’ ...
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C8051F80x-83x SFR Definition 23.1. XBR0: Port I/O Crossbar Register 0 Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xE1 Bit Name 7:6 Unused Read = 00b. Write = don’t care. 5 CP0AE Comparator0 Asynchronous Output ...
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SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1 Bit 7 6 Name WEAKPUD XBARE R/W R/W Type 0 0 Reset SFR Address = 0xE2 Bit Name 7 WEAKPUD Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for ...
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C8051F80x-83x 23.5. Port Match Port match functionality allows system events to be triggered by a logic value change P1. A soft- ware controlled value stored in the PnMATCH registers specifies the expected or normal logic values of ...
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SFR Definition 23.3. P0MASK: Port 0 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xFE Bit Name 7:0 P0MASK[7:0] Port 0 Mask Value. Selects P0 pins to be compared to the corresponding bits in P0MAT. ...
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C8051F80x-83x SFR Definition 23.5. P1MASK: Port 1 Mask Register Bit 7 6 Name Type 0 0 Reset SFR Address = 0xEE Bit Name 7:0 P1MASK[7:0] Port 1 Mask Value. Selects P1 pins to be compared to the corresponding bits in ...
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Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig- ital functions or skipped by the Crossbar. All Port pins used for analog functions or GPIO should have their PnSKIP bit set ...
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C8051F80x-83x SFR Definition 23.8. P0MDIN: Port 0 Input Mode Bit 7 6 Name Type 1 1 Reset SFR Address = 0xF1 Bit Name 7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 23.10. P0SKIP: Port 0 Skip Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD4 Bit Name 7:0 P0SKIP[7:0] Port 0 Crossbar Skip Enable Bits. These bits select Port 0 pins to be skipped by the ...
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C8051F80x-83x SFR Definition 23.12. P1MDIN: Port 1 Input Mode Bit 7 6 Name Type 1* 1* Reset SFR Address = 0xF2 Bit Name 7:0 P1MDIN[7:0] Analog Configuration Bits for P1.7–P1.0 (respectively). Port pins configured for analog mode have their weak ...
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SFR Definition 23.14. P1SKIP: Port 1 Skip Bit 7 6 Name Type 0* 0* Reset SFR Address = 0xD5 Bit Name 7:0 P1SKIP[7:0] Port 1 Crossbar Skip Enable Bits. These bits select Port 1 pins to be skipped by the ...
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C8051F80x-83x SFR Definition 23.16. P2MDOUT: Port 2 Output Mode Bit 7 6 Name R R Type 0 0 Reset SFR Address = 0xA6 Bit Name 7:1 Unused Read = 0000000b; Write = Don’t Care 0 P2MDOUT[0] Output Configuration Bits for ...
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Cyclic Redundancy Check Unit (CRC0) C8051F80x-83x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts ...
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C8051F80x-83x 24.1. 16-bit CRC Algorithm The C8051F80x-83x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following describes the 16-bit CRC algorithm performed by the hardware: 1. XOR the most-significant byte of the current CRC result ...
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CRC Algorithm The C8051F80x-83x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algo- rithm is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the pro- ...
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C8051F80x-83x 24.3. Preparing for a CRC Calculation To prepare CRC0 for a CRC calculation, software should select the desired polynomial and set the initial value of the result. Two polynomials are available: 0x1021 (16-bit) and 0x04C11DB7 (32-bit). The CRC0 result ...
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SFR Definition 24.1. CRC0CN: CRC0 Control Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xCE Bit Name 7:5 Unused Read = 000b; Write = Don’t Care. 4 CRC0SEL CRC0 Polynomial Select Bit. This bit selects ...
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C8051F80x-83x SFR Definition 24.2. CRC0IN: CRC Data Input Bit 7 6 Name Type 0 0 Reset SFR Address = 0xDD Bit Name 7:0 CRC0IN[7:0] CRC0 Data Input. Each write to CRC0IN results in the written data being computed into the ...
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SFR Definition 24.4. CRC0AUTO: CRC Automatic Control Bit 7 6 AUTOEN CRCCPT Reserved Name Type 0 1 Reset SFR Address = 0xD2 Bit Name 7 AUTOEN Automatic CRC Calculation Enable. When AUTOEN is set to 1, any write to CRC0CN ...
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C8051F80x-83x 24.6. CRC0 Bit Reverse Feature CRC0 includes hardware to reverse the bit order of each bit in a byte as shown in Figure 24.1. Each byte of data written to CRC0FLIP is read back bit reversed. For example, if ...
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Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...
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C8051F80x-83x 25.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 25.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
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While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. ...
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C8051F80x-83x Master Device GPIO Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram 25.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave ...
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SPI0 Interrupt Sources When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1: All of the following bits must be cleared by software. The SPI Interrupt Flag, SPIF ...
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C8051F80x-83x SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB NSS (Must Remain High in Multi-Master Mode) Figure 25.5. Master Mode Data/Clock Timing SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire ...
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SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 25.7. Slave Mode Data/Clock Timing (CKPHA = 1) 25.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system ...
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C8051F80x-83x SFR Definition 25.1. SPI0CFG: SPI0 Configuration Bit 7 6 SPIBSY MSTEN CKPHA Name R R/W Type 0 0 Reset SFR Address = 0xA1 Bit Name 7 SPIBSY SPI Busy. This bit is set to logic 1 when a SPI ...
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SFR Definition 25.2. SPI0CN: SPI0 Control Bit 7 6 SPIF WCOL MODF Name R/W R/W Type 0 0 Reset SFR Address = 0xF8; Bit-Addressable Bit Name 7 SPIF SPI0 Interrupt Flag. This bit is set to logic 1 by hardware ...
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C8051F80x-83x SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate Bit 7 6 Name Type 0 0 Reset SFR Address = 0xA2 Bit Name 7:0 SCR[7:0] SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module ...
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SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 25.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
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C8051F80x-83x NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 25.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...
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Table 25.1. SPI Slave Timing Parameters Parameter Description Master Mode Timing (See Figure 25.8 and Figure 25.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge to ...
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C8051F80x-83x 26. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with ...
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Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification—Version 2.0, ...
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C8051F80x-83x All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE ...
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SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 26.3.5. SCL High (SMBus Free) Timeout The SMBus specification ...
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C8051F80x-83x Table 26.1. SMBus Clock Source Selection SMBCS1 The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as ...
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EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Table 26.2. Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time T low 0 ...
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C8051F80x-83x SFR Definition 26.1. SMB0CF: SMBus Clock/Configuration Bit 7 6 ENSMB INH Name R/W R/W Type 0 0 Reset SFR Address = 0xC1 Bit Name 7 ENSMB SMBus Enable. This bit enables the SMBus interface when set to 1. When ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 26.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
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C8051F80x-83x SFR Definition 26.2. SMB0CN: SMBus Control Bit 7 6 MASTER TXMODE Name R R Type 0 0 Reset SFR Address = 0xC0; Bit-Addressable Bit Name Description 7 MASTER SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is ...
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Table 26.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: A START is generated. MASTER START is generated. SMB0DAT is written before the start of an TXMODE SMBus frame. A START followed by ...
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C8051F80x-83x case, either value are acceptable on the incoming slave address. Additionally, if the GC bit in register SMB0ADR is set to 1, hardware will recognize the General Call Address (0x00). Table 26.4 shows some ...
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SFR Definition 26.3. SMB0ADR: SMBus Slave Address Bit 7 6 Name Type 0 0 Reset SFR Address = 0xD7 Bit Name 7:1 SLV[6:0] SMBus Hardware Slave Address. Defines the SMBus Slave Address(es) for automatic hardware acknowledgement. Only address bits which ...
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C8051F80x-83x 26.4.4. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F80x-83x 26.5.2. Read Sequence (Master) During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will be a transmitter during the address byte, and a receiver during all data bytes. The SMBus ...
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Write Sequence (Slave) During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. When slave events ...
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C8051F80x-83x 26.5.4. Read Sequence (Slave) During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. When slave ...
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Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK ...
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C8051F80x-83x Table 26.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. ...
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Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) Values Read Current SMbus State A master START was gener- 1110 ated. A master data or address byte was transmitted; NACK ...
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C8051F80x-83x Table 26.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. ...