C8051F353-GM Silicon Laboratories Inc, C8051F353-GM Datasheet - Page 115
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C8051F353-GM
Manufacturer Part Number
C8051F353-GM
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 16-bit
On-chip Dac
2-ch x 8-bit
No. Of I/o's
17
Ram Memory Size
768Byte
Cpu Speed
50MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
28QFN
Device Core
8051
Family Name
C8051F35x
Maximum Speed
50 MHz
Data Rom Size
128 B
Height
0.88 mm
Length
5 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1083 - DEV KIT FOR F350/351/352/353
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1273
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F353-GM
Manufacturer:
SiliconL
Quantity:
8 050
14. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pull-ups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “17. Oscillators’ on page 129 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (Section “23.3. Watchdog Timer Mode’ on page 220 details the use of the Watchdog Timer). Pro-
gram execution begins at location 0x0000.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Px.x
Px.x
System
Clock
Comparator 0
+
-
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
DD
Extended Interrupt
Monitor and power-on resets, the /RST pin is driven low until the device
CIP-51
Handler
Core
Figure 14.1. Reset Sources
WDT
PCA
EN
VDD
System Reset
Supply
Monitor
+
-
Rev. 1.1
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
C8051F350/1/2/3
Operation
FLASH
Errant
(wired-OR)
Reset
Funnel
/RST
115