MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 21

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)
3. This signal is also brought out on the GPIOB7 pin.
4. This signal is also brought out on the GPIOB6 pin.
Return to
(GPIOD1)
GPIOB0
GPIOB1
(SCLK)
(SDA
(SCL
Signal
Name
TDO
(SS)
3
4
)
)
Table 2-2
Pin No.
LQFP
32
21
2
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
State During
Input with
Input with
enabled
enabled
internal
internal
56F8013/56F8011 Data Sheet, Rev. 12
Output
pull-up
pull-up
Reset
Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDO.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SPI Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Serial Data — This pin serves as the I
After reset, the default state is GPIOB0. The alternative peripheral
functionality is controlled via the SIM. See
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
SPI Slave Select — SS is used in slave mode to indicate to the SPI
module that the current transfer is to be received.
Serial Clock — This pin serves as the I
After reset, the default state is GPIOB1. The alternative peripheral
functionality is controlled via the SIM. See
Signal Description
2
C serial clock.
2
C serial data line.
Section
Section
56F8013/56F8011 Signal Pins
6.3.8.
6.3.8.
21