mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet
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mc56f801 Summary of contents
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... Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8014 Rev. 9 01/2007 freescale.com ...
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Version History Rev 0 Initial release Rev 1 Updates to Table 10-1, added maximum clamp current, per pin Table 10-11, clarified variation over temperature table and graph Table 10-15, added LIN slave timing Rev 2 Added alternate pins to Rev ...
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Document Revision History (Continued) Version History Rev. 9 Added the following note to the description of the TMS signal in Note: Always tie the TMS pin to V Please see http://www.freescale.com for the most current data sheet revision. Freescale Semiconductor ...
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General Description • MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 16KB Program Flash • 4KB Unified Data/Program RAM • One 5-channel PWM module • Two 4-channel 12-bit ...
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Data Sheet Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 6 1.1. 56F8014 Features . . . . ...
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Part 1 Overview 1.1 56F8014 Features 1.1.1 Digital Signal Controller Core • Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture • As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency Single-cycle ...
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Taking into account values setting ADC high- and low-limit registers, each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – External GPIO – Internal timers – ADC conversion result • Two independent ...
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Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available • ADC smart power management • Each ...
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This Digital Signal Controller also provides a full set of standard programmable peripherals that include one Serial Communications Interface (SCI), one Serial Peripheral Interface (SPI), one Quad Timer, and 2 one Inter-Integrated Circuit (I Input/Outputs (GPIOs). 1.3 Award-Winning Development Environment ...
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Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Bit- Manipulation Unit Enhanced OnCE™ JTAG TAP Figure 1-1 56800E Core Block Diagram 10 DSP56800E Core Address Generation Instruction Unit Decoder (AGU) Interrupt M01 Unit N3 ...
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CLKGEN (ROSC / PLL / CLKIN) 8 GPIO A GPIOAn 8 GPIO B GPIOBn 6 GPIOCn GPIO C 4 GPIODn GPIO D Freescale Semiconductor Preliminary To/From IPBus Bridge IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8014 Technical Data, ...
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Figure 1-2) To/From IPBus Bridge PWM Output Controls Reload 3 2 Pulse from ADC T3i T2/3 Timer T2o, T3o muxed with both SPI and SCI. T2 and T3 are muxed with SPI and PWM. ...
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... Description Logic State True False True False are defined by individual product specifications. 56F8014 Technical Data, Rev. 9 Product Documentation Order Number DSP56800ERM MC56F8000RM 56F801xBLUG MC56F8014 MC56F8014E Signal State 1 Voltage Asserted Deasserted Asserted ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8014 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In signals present on a pin, sorted by pin number. ...
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LQFP Pin Signal Name Pin # Name 1 GPIOB1 GPIOB1, SS, SDA 2 GPIOB7 GPIOB7, TXD, SCL 3 GPIOB5 GPIOB5, T1, FAULT3 4 ANB0 ANB0, GPIOC4 5 ANB1 ANB1, GPIOC5 6 ANB2 ANB2 REFL GPIOC6 7 ANB3 ANB3, ...
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LQFP Pin Signal Name Pin # Name 25 VDD_IO V DD_IO 26 VSS_IO V SS_IO 27 GPIOA1 GPIOA1, PWM1 28 GPIOA0 GPIOA0, PWM0 29 TDI TDI, GPIOD0 30 TMS TMS, GPIOD3 31 TDO TDO, GPIOD1 32 GPIOB6 GPIOB6, RXD, SDA, ...
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Power Ground Power Ground Other Supply Ports GPIOB6 (RXD, SDA, CLKIN) SCI Port Port or GPIOB7 (TXD, SCL) GPIO RESET RESET (GPIOA7) GPIOB4 (T0, CLKO) Timer Port or GPIO GPIOB5 (T1, FAULT3) TCK (GPIOD2) TMS (GPIOD3) ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP Signal LQFP Type Name Pin No. V ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. GPIOB7 2 Input/ Output (TXD) Input/ Output 2 Input/ (SCL ) Output 2. This signal is also brought out on the GPIOB0 ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. GPIOB5 3 Input/ Output (T1) Input/ Output (FAULT3) Output TCK 15 Input (GPIOD2) Input/ Output TMS 30 Input (GPIOD3) Input/ Output TDI ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. TDO 31 Output (GPIOD1) Input/ Output GPIOB0 21 Input/ Output (SCLK) Input/ Output Input/ 3 (SCL ) Output 3. This signal is ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. GPIOB2 18 Input/ Output (MISO) Input/ Output Input/ 5 (T2 ) Output 5. This signal is also brought out on the GPIOA4 ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. GPIOA1 27 Input/ Output (PWM1) Output GPIOA2 23 Input/ Output (PWM2) Output GPIOA4 22 Input/ Output (PWM4) Output (FAULT1) Input Input/ 7 ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. ANA0 13 Input (GPIOC0) Input/ Output ANA1 12 Input (GPIOC1) Input/ Output ANA2 11 Input (V ) Input REFH Input/ (GPIOC2) Output ...
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Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued) Signal LQFP Type Name Pin No. ANB1 5 Input (GPIOC5) Input/ Output ANB2 6 Input (V ) Input REFL Input/ (GPIOC6) Output ANB3 7 Input (GPIOC7) Input/ Output ...
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Part 3 OCCS 3.1 Overview This module provides the 2X system clock frequency to the System Integration Module (SIM), which uses it to generate the various chip clocks. This module also produces the OSC_CLK signals plus the ADC clock and ...
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The 56F801X family parts’ on-chip clock synthesis module has the following registers: • Control Register (OCCS_CR) • Divide-by Register (OCCS_DB) • Status Register (OCCS_SR) • Shutdown Register (OCCS_SHUTDN) • Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please ...
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Block Diagram Figure 3-2 provides a block diagram which shows how the 56F8014 creates its internal clock, using the relaxation oscillator as an 8MHz clock reference for the PLL. Relaxation OSC GPIOB6 / RXD MUX FOUT PLL X 24 ...
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Pin Descriptions 3.5.1 External Reference (GPIOB6 / RXD) The relaxation oscillator is included on chip and the reset mode is to use this as the clock source for the chip. The user then has the option of switching to ...
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Table 4-2 Interrupt Vector Table Contents Vector Priority Peripheral Number Level core core core 2 3 core 3 3 core 4 3 core 5 3 core 6 1-3 core 7 1-3 core 8 1-3 core 9 1-3 core 10 1-3 ...
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Table 4-2 Interrupt Vector Table Contents Vector Priority Peripheral Number Level Timer 38 0-2 Timer 39 0-2 ADC 40 0-2 ADC 41 0-2 ADC 42 0-2 PWM 43 0-2 PWM 44 0-2 SWILP Two words are allocated ...
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Data Map Begin/End Address X:$FF FFFF X:$FF FF00 X:$FF FEFF X:$01 0000 X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 8800 X:$00 EFFF X:$00 0800 X:$00 7FFF X:$00 0040 X:$00 07FF X:$00 0000 1. All addresses are 16-bit Word addresses. ...
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Address Register Acronym X:$FF FFFF OTX1 / ORX1 X:$FF FFFE OTX / ORX (32 bits) X:$FF FFFD OTXRXSR X:$FF FFFC OCLSR X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 OCR X:$FF FF9F X:$FF FF9E OSCNTR (24 bits) X:$FF FF9D OSR X:$FF ...
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The following tables list all of the peripheral registers required to control or access the peripherals. Table 4-6 Data Memory Peripheral Base Address Map Summary Peripheral Timer PWM ITCN ADC SCI SPI COP CLK, PLL, OSC, TEST ...
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Table 4-7 Quad Timer Registers Address Map (Continued) Register Acronym TMR1_CAPT TMR1_LOAD TMR1_HOLD TMR1_CNTR TMR1_CTRL TMR1_SCTRL TMR1_CMPLD1 TMR1_CMPLD2 TMR1_CSCTRL TMR2_COMP1 TMR2_COMP2 TMR2_CAPT TMR2_LOAD TMR2_HOLD TMR2_CNTR TMR2_CTRL TMR2_SCTRL TMR2_CMPLD1 TMR2_CMPLD2 TMR2_CSCTRL TMR3_COMP1 TMR3_COMP2 TMR3_CAPT TMR3_LOAD TMR3_HOLD TMR3_CNTR TMR3_CTRL TMR3_SCTRL TMR3_CMPLD1 TMR3_CMPLD2 ...
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Table 4-8 Pulse Width Modulator Registers Address Map Register Acronym PWM_CTRL PWM_FCTRL PWM_FLTACK PWM_OUT PWM_CNTR PWM_CMOD PWM_VAL0 PWM_VAL1 PWM_VAL2 PWM_VAL3 PWM_VAL4 PWM_VAL5 PWM_DTIM0 PWM_DTIM1 PWM_DMAP1 PWM_DMAP2 PWM_CNFG PWM_CCTRL PWM_PORT PWM_ICCTRL PWM_SCTRL Table 4-9 Interrupt Control Registers Address Map Register Acronym ...
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Table 4-9 Interrupt Control Registers Address Map (Continued) Register Acronym ITCN_FIM1 ITCN_FIVAL1 ITCN_FIVAH1 ITCN_IRQP 0 ITCN_IRQP 1 ITCN_IRQP 2 ITCN_ICTRL Table 4-10 Analog-to-Digital Converter Registers Address Map Register Acronym ADC_CTRL1 ADC_CTRL2 ADC_ZXCTRL ADC_CLIST 1 ADC_CLIST 2 ADC_SDIS ADC_STAT ADC_LIMSTAT ADC_ZXSTAT ...
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Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADC_LOLIM6 ADC_LOLIM7 ADC_HILIM0 ADC_HILIM1 ADC_HILIM2 ADC_HILIM3 ADC_HILIM4 ADC_HILIM5 ADC_HILIM6 ADC_HILIM7 ADC_OFFST0 ADC_OFFST1 ADC_OFFST2 ADC_OFFST3 ADC_OFFST4 ADC_OFFST5 ADC_OFFST6 ADC_OFFST7 ADC_PWR ADC_VREF Table 4-11 Serial Communication Interface Registers Address Map Register Acronym ...
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Table 4-12 Serial Peripheral Interface Registers Address Map Register Acronym SPI_SCTRL SPI_DSCTRL SPI_DRCV SPI_DXMIT Table 4-13 I Register Acronym I2C_ADDR I2C_FDIV I2C_CTRL I2C_STAT I2C_DATA I2C_NFILT Table 4-14 Computer Operating Properly Registers Address Map Register Acronym COP_CTRL COP_TOUT COP_CNTR Table 4-15 ...
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Table 4-16 GPIOA Registers Address Map Register Acronym GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Table 4-17 GPIOB Registers Address Map Register Acronym GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE ...
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Table 4-18 GPIOC Registers Address Map Register Acronym GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Table 4-19 GPIOD Registers Address Map Register Acronym GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE ...
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Table 4-20 System Integration Module Registers Address Map Register Acronym SIM_CTRL SIM_RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR SIM_CLKOUT SIM_GPS SIM_PCE SIM_IOSAHI SIM_IOSALO Table 4-21 Power Supervisor Registers Address Map Register Acronym PS_CTRL PS_STAT Table 4-22 Flash Module Registers ...
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Table 4-22 Flash Module Registers Address Map (Continued) Register Acronym FM_USTAT FM_CMD FM_DATA FM_OPT1 FM_TSTSIG Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to signal to the ...
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Normal Interrupt Handling Once the INTC has determined that an interrupt serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the ...
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Block Diagram Priority Level 2 -> 4 INT0 Decode Priority Level 2 -> 4 INT45 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Base Address + Acronym IPR0 $0 IPR1 $1 IPR2 $2 IPR3 $3 IPR4 $4 VBA $5 FIM0 $6 FIVAL0 $7 FIVAH0 $8 FIM1 $9 FIVAL1 $A FIVAH1 $B IRQP0 $C IRQP1 $D IRQP2 $E ICTRL $12 46 Table 5-2 ...
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Add. Register 15 14 Offset Name R $0 IPR0 LVI IPL IPR1 GPIOB IPL W R SCI_RCV $2 IPR2 IPL W R ADCA_CC $3 IPR3 IPL IPR4 ...
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LVI IPL—Bits 15–14 This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities 0 through 2 and is disabled by default. • IRQ disabled (default) • 01 ...
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EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • ...
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GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) ...
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PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled ...
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SCI Transmitter Idle Interrupt Priority Level (SCI_TIDL IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • ...
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GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 1–0 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) ...
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Timer Channel 1 Interrupt Priority Level (TMR_1 IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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PWM Fault Interrupt Priority Level (PWM_F IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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Vector Base Address Register (VBA) Base + $ Read 0 0 Write RESET Figure 5-8 Vector Base Address Register (VBA) 5.6.6.1 Reserved—Bits15—14 This bit field is reserved or not implemented read ...
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Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15—0 The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in ...
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Fast Interrupt 1 Vector Address Low Register (FIVAL1) Base + $ Read Write RESET Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1) 5.6.11.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 ...
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IRQ Pending Register 1 (IRQP1) Base + $ Read Write RESET Figure 5-16 IRQ Pending Register 1 (IRQP1) 5.6.14.1 IRQ Pending (PENDING)—Bits 32–17 This register combines with IRQP0 and IRQP2 to represent the ...
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Interrupt Priority Level (IPIC)—Bits 14–13 These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E core. These bits indicate the priority level needed for a new IRQ to interrupt the current ...
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Resets 5.7.1 General Reset Core Reset 5.7.2 Description of Reset Operation 5.7.2.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset ...
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Part 6 System Integration Module (SIM) 6.1 Introduction The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The System ...
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Register Descriptions Table 6-1 SIM Registers (SIM_BASE = $00 F140) Address Offset Address Acronym Base + $0 SIM_CTRL Base + $1 SIM_RSTAT Base + $2 SIM_SWC0 Base + $3 SIM_SWC1 Base + $4 SIM_SWC2 Base + $5 SIM_SWC3 Base ...
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Add. Address Offset Acronym SIM_ TC3_ TC2_ $0 CTRL SIM_ $1 RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 ...
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Timer Channel 2 Stop Disable (TC2_SD)—Bit 14 This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode. • Timer Channel 2 disabled in Stop mode • Timer Channel 2 enabled ...
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Stop Disable (STOP_DISABLE[1:0])—Bits 3–2 • Stop mode will be entered when the 56800E core executes a STOP instruction • The 56800E STOP instruction will not cause entry into Stop mode • Stop mode ...
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External Reset (EXTR)—Bit 3 When set, this bit indicates that the previous system reset was caused by an external reset. It will only be set if the external reset pin was asserted or remained asserted after the Power-On Reset ...
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Base + $ Read Write RESET Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID) 6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large regulator. ...
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Base + $ Read Write RESET Figure 6-8 CLKO Select Register (SIM_CLKOUT) 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved or not implemented read as 0 and cannot be ...
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SIM GPIO Peripheral Select Register (SIM_GPS) All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. In order to select peripheral or GPIO control, program the GPIOx_PEREN register. In some cases, there are two ...
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PWM Clock Rate (PCR)—Bit 14 This bit selects the clock speed for the PWM module. • PWM module clock rate equals core clock rate, typically 32MHz (default) • PWM module clock rate equals three times ...
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Configure GPIOB5 (CFG_B5)—Bit 9 This bit selects the alternate function for GPIOB5. • (default) • FAULT3 6.3.8.7 Configure GPIOB4 (CFG_B4)—Bit 8 This bit selects the alternate function for GPIOB4. • (default) ...
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Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0 These bits select the alternate function for GPIOA4. • Select PWM4 when peripheral mode is enabled in GPIOA4 (default) • Select PWM4 when peripheral mode is enabled in GPIOA4 • 10 ...
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Reserved—Bit 5 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.3.9.7 SCI IPBus Clock Enable (SCI)—Bit 4 Each bit controls clocks to the indicated peripheral. • ...
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Bits from SIM_IOSALO Register 2 bits from SIM_IOSAHI Register Full 24-Bit for Short I/O Address Figure 6-12 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral ...
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Base + $ Read Write RESET Figure 6-14 I/O Short Address Location Low Register (SIM_IOSALO) 6.3.10.3 Input/Output Short Address Location (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” ...
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Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Run Core and memory clocks disabled Wait Core and memory clocks disabled Stop Master clock generation in the OCCS remains operational, but the SIM disables the generation of system and ...
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Standby 200kHz system bus rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the part and minimizes its power utilization but is only recoverable via reset. When the PLL is not selected and ...
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POR Power-On Reset pulse shaper (active Delay 64 low) MSTR_OSC Clocks COMBINED_RST External RESET IN RESET (active low) COP (active SW Reset low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles. Figure 6-15 Sources ...
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Clocks The memory, peripheral and core clocks all operate at the same frequency (32MHz max) with the exception of the TMR and PWM peripheral clocks, which have the option (using TCR and PCR) to operate three times faster. The ...
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Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles RST MSTR_OSC CKGEN_RST SYS_CLK_x2 SYS_CLK SYS_CLK_D SYS_CLK_DIV2 PERIP_RST CORE_RST Figure 6-16 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts. Part ...
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Operation with Security Enabled Once the user has programmed the Flash with his application code, the 56F8014 can be secured by programming the security bytes located in the FM configuration field, which are located at the last 9 words ...
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Flash Lockout Recovery using CodeWarrior CodeWarrior can unlock a device using the command sequence described in Section 7.2.2 by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the ...
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Table 8-2 GPIO External Signals Map Pins in shaded rows are not available in 56F8014 GPIO Function Peripheral Function GPIOA0 PWM0 GPIOA1 PWM1 GPIOA2 PWM2 GPIOA3 PWM3 GPIOA4 PWM4 / FAULT1 / T2 GPIOA5 PWM5 / FAULT2 / T3 GPIOA6 ...
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Table 8-2 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8014 GPIO Function Peripheral Function GPIOB6 RXD / SDA / CLKIN GPIOB7 TXD / SCL GPIOC0 ANA0 GPIOC1 ANA1 GPIOC2 ANA2 / V GPIOC3 ANA3 ...
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Add. Register Acronym 15 Offset GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT ...
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Add. Register Acronym 15 Offset GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT ...
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Add. Register Acronym 15 Offset GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT ...
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Add. Register Acronym 15 Offset GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT ...
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Part 9 Joint Test Action Group (JTAG) 9.1 56F8014 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to V The JTAG ...
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Table 10-1 Absolute Maximum Ratings Characteristic Supply Voltage Range Analog Supply Voltage Range ADC High Voltage Reference Voltage difference DD_IO DDA Voltage difference SS_IO SSA Input Voltage Range (Digital inputs) 1 Input Voltage Range ...
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Table 10-3 LQFP Package Thermal Characteristics Characteristic Junction to ambient Natural convection Junction to ambient Natural convection Junction to ambient (@200 ft/min) Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to package top 1. Junction temperature ...
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Table 10-4 Recommended Operating Conditions Characteristic Supply voltage ADC Supply voltage ADC High Voltage Reference Voltage difference DD_IO DDA Voltage difference SS_IO SSA Device Clock Frequency Using relaxation oscillator Using external clock source Input ...
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DC Electrical Characteristics Table 10-5 DC Electrical Characteristics Characteristic Output Voltage High Output Voltage Low Digital Input Current High 1 pull-up enabled or disabled Digital Input Current Low pull-up enabled 1 pull-up disabled Output Current 1 High Impedance State ...
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Table 10-6 Current Consumption per Power Supply Pin (Typical) Mode RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled. TMR and PWM using 1x Clock ADC powered ...
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Table 10-7 Power-On Reset Low-Voltage Parameters Characteristic Low-Voltage Interrupt for 3.3V supply Low-Voltage Interrupt for 2.5V supply Low-Voltage Interrupt Recovery Hysteresis 3 Power-On Reset 1. When V drops below When V drops below Power-On ...
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Input Signal Midpoint1 Fall Time Note: The midpoint Figure 10-2 Input Signal Measurement References Figure 10-3 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and ...
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External Clock Operation Timing Table 10-10 External Clock Operation Timing Requirements Characteristic Frequency of operation (external clock driver) 3 Clock Pulse Width External Clock Input Rise Time 5 External Clock Input Fall Time 1. Parameters listed are guaranteed by ...
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Relaxation Oscillator Timing Table 10-12 Relaxation Oscillator Timing Characteristic Relaxation Oscillator output frequency Normal Mode Standby Mode Relaxation Oscillator stabilization time Cycle-to-cycle jitter. This is measured on the CLKO signal (programmed prescaler_clock) 3 over 264 clocks Minimum tuning step ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All the address and data buses described here are internal. Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic Minimum RESET Assertion Duration Minimum GPIO pin Assertion for ...
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Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 32MHz operation 31.25ns. 2. ...
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Serial Communication Interface (SCI) Timing Characteristic 2 Baud Rate 3 RXD Pulse Width 4 TXD Pulse Width Deviation of slave node clock from nominal clock rate before synchronization Deviation of slave node clock relative to the master node clock ...
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Inter-Integrated Circuit Interface (I Characteristic SCL Clock Frequency Hold time (repeated ) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a ...
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SDA t LOW SCL t HD; STA S t HD; DAT Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I 10.13 JTAG Timing Characteristic 1 TCK frequency of operation TCK clock pulse width TMS, TDI data ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) Figure 10-16 Test Access Port Timing Diagram 108 t DS Input Data Valid t DV Output Data Valid t TS 56F8014 Technical Data, Rev Freescale Semiconductor Preliminary ...
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Analog-to-Digital Converter (ADC) Parameters Parameter DC Specifications Resolution ADC internal clock Conversion range 2 ADC power-up time Recovery from auto standby Conversion time Sample time Accuracy 4 Integral non-linearity (Full input signal range) Differential non-linearity Monotonicity Offset Voltage Internal ...
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Equivalent Circuit for ADC Inputs Figure 10-17 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
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A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency. B, the internal [state-dependent component], reflects the supply current ...
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Part 11 Packaging 11.1 56F8014 Package and Pin-Out Information This section contains package and pin-out information for the 56F8014. This device comes in a 32-pin Low-profile Quad Flat Pack (LQFP). Figure 11-2 shows the mechanical parameters for this package, and ...
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Table 11-1 56F8014 32-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 GPIOB1 9 SS,SDA 2 GPIOB7 10 TXD,SCL 3 GPIOB5 11 T1,FAULT3 4 ANB0 12 GPIOC4 5 ANB1 13 GPIOC5 6 ANB2 14 V ...
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–T– DETAIL –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD Figure 11-2 56F8014 32-Pin LQFP Mechanical Information Please see http://www.freescale.com ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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Take special care to minimize noise levels on the V • Using separate power planes for V recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog ...
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... Table 13-1 56F8014 Ordering Information Supply Part Voltage Low-Profile Quad Flat Pack (LQFP) MC56F8014 3.0–3.6 V *This package is RoHS compliant. 118 Pin Frequency Package Type Count 32 56F8014 Technical Data, Rev. 9 Abient Temperature Order Number (MHz) Range 32 -40° 105° C MC56F8014VFAE* Freescale Semiconductor Preliminary ...
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Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table. Module Register Name ADC Control Register 1 Control ...
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Module Register Name FM Clock Divider Register Configuration Register Security High Half Register Security Low Half Register Protection Register User Status Register Command Register Address Register Data Buffer Register Optional Data 1 Register Test Array Signature Register GPIO Pull-Up Enable ...
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Module Register Name SIM Control Register Reset Status Register Software Control Register 0-3 Most Significant Half JTAG ID Least Significant Half JTAG ID Power Control Register Clock Out Select Register GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short ...
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Technical Data, Rev. 9 Freescale Semiconductor Preliminary ...
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Freescale Semiconductor Preliminary 56F8014 Technical Data, Rev. 9 Electrical Design Considerations 123 ...
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Technical Data, Rev. 9 Freescale Semiconductor Preliminary ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. MC56F8014 Rev. 9 01/2007 ...