mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 19

• Manufacturer Part Number: mc56f801
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Preliminary
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
2. This signal is also brought out on the GPIOB0 pin.
Return to
(GPIOA7)
GPIOB7
GPIOB4
(CLKO)
RESET
Signal
(SCL
Name
(TXD)
(T0)
2
)
Table 2-2
Pin No.
LQFP
16
19
2
Input/Open
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Type
Drain
Input
State During
pin is in input
pin is in input
pin is in input
disabled,
disabled,
disabled,
enabled,
enabled,
enabled,
internal
internal
internal
Output
pull-up
Output
pull-up
Output
pull-up
Reset
mode
mode
mode
56F8014 Technical Data, Rev. 9
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Transmit Data — SCI transmit data output or transmit / receive in
single wire opeation.
Serial Clock — This pin serves as the I
After reset, the default state is GPIOB7. The peripheral functionality
is controlled via the SIM. See
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
T0 — Timer, Channel 0
Clock Output — This is a buffered clock signal. Using the
SIM_CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled (logic 0), CLK_MSTR
(system clock), IPBus clock, or oscillator output. See
After reset, the default state is GPIOB4. The peripheral functionality
is controlled via the SIM. See
Signal Description
Section
Section
6.3.8.
6.3.8.
2
C serial clock.
Section
56F8014 Signal Pins
6.3.7.
19