mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 45

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mc56f801

Manufacturer Part Number
mc56f801
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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5.4 Block Diagram
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level. The ITCN module has 16 registers.
Freescale Semiconductor
Preliminary
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
INT0
INT45
Decode
Decode
Priority
Priority
Level
Level
2 -> 4
2 -> 4
Figure 5-1 Interrupt Controller Block Diagram
56F8014 Technical Data, Rev. 9
Level 0
Level 3
Encoder
Encoder
Priority
Priority
46 -> 6
46 -> 6
6
6
any0
any3
IACK
SR[9:8]
CONTROL
PIC_EN
INT
VAB
IPIC
Block Diagram
45

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