MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 68

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.1.2
This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.
6.3.1.3
This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.
6.3.1.4
This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.
6.3.1.5
This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in
LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is
in Sleep mode and using Stop mode to reduce power consumption.
6.3.1.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.7
This bit selects the input of Timer Channel 3 to be from the PWM Sync signal or GPIO pin.
6.3.1.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.9
6.3.1.10
Writing 1 to this field will cause the part to reset.
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1 = Timer Channel 3 enabled in Stop mode
0 = Timer Channel 2 disabled in Stop mode
1 = Timer Channel 2 enabled in Stop mode
0 = Timer Channel 1 disabled in Stop mode
1 = Timer Channel 1 enabled in Stop mode
0 = Timer Channel 0 disabled in Stop mode
1 = Timer Channel 0 enabled in Stop mode
0 = SCI disabled in Stop mode
1 = SCI enabled in Stop mode
1 = Timer Channel 3 Input from PWM sync signal
0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Timer Channel 2 Stop Disable (TC2_SD)—Bit 14
Timer Channel 1 Stop Disable (TC1_SD)—Bit 13
Timer Channel 0 Stop Disable (TC0_SD)—Bit 12
SCI Stop Disable (SCI_SD)—Bit 11
Reserved—Bit 10
Timer Channel 3 Input (TC3_INP)—Bit 9
Reserved—Bits 8–6
OnCE Enable (ONCEEBL)—Bit 5
Software Reset (SWRST)—Bit 4
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor