C8051F34A-GM Silicon Laboratories Inc, C8051F34A-GM Datasheet - Page 174

IC 8051 MCU 64K FLASH MEM 32-QFN

C8051F34A-GM

Manufacturer Part Number
C8051F34A-GM
Description
IC 8051 MCU 64K FLASH MEM 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheet

Specifications of C8051F34A-GM

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4352 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
32QFN EP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Cpu Family
C8051F34x
Device Core Size
8b
Frequency (max)
48MHz
Total Internal Ram Size
4.25KB
# I/os (max)
25
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
QFN EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1350-5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
174
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hard-
ware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hard-
ware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
USB Register Definition 16.13. CMINT: USB0 Common Interrupt
Bit6
R
-
Bit5
R
-
Bit4
R
-
Rev. 1.3
SOF
Bit3
R
RSTINT
Bit2
R
RSUINT
Bit1
R
SUSINT
Bit0
R
USB Address:
00000000
Reset Value
0x06

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