M30627FJPGP#U7C Renesas Electronics America, M30627FJPGP#U7C Datasheet - Page 112
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123038/m30627fjpgp_u7c_sml.jpg)
M30627FJPGP#U7C
Manufacturer Part Number
M30627FJPGP#U7C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U7CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 10.3
NOTES:
PLL Operating Mode
High-Speed Mode
Medium-
Speed Mode
Low-Speed Mode
Low Power Dissipation Mode
On-chip
Oscillator
Mode
On-chip Oscillator Low Power
Dissipation Mode
10.4.1.7
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low
2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in
the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks.
If the sub clock is on, fC32 can be used as the count source for Timers A and B.
power dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.
Jan 10, 2006
Modes
On-chip Oscillator Low Power Dissipation Mode
Setting Clock Related Bit and Modes
divided by 2
divided by 4
divided by 8
divided by 16
divided by 1
divided by 2
divided by 4
divided by 8
divided by 16
Page 95 of 390
Register
CM21
CM2
0
0
0
0
0
0
−
0
1
1
1
1
1
1
CM11
1
0
0
0
0
0
0
0
0
0
0
0
0
0
CM1 Register
CM17, CM16
(NOTE 2)
00b
00b
01b
10b
11b
00b
01b
10b
11b
−
−
−
-
CM07
0
0
0
0
0
0
1
1
0
0
0
0
0
0
(NOTE 2)
CM06
1
CM0 Register
0
0
0
0
1
0
−
0
0
0
1
0
(1)
10. Clock Generation Circuit
CM05
1
0
0
0
0
0
0
0
0
0
0
0
0
1
(1)
− : “0” or ”1”
CM04
−
−
−
−
−
−
1
1
−
−
−
−
−
−
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