M30627FJPGP#U7C Renesas Electronics America, M30627FJPGP#U7C Datasheet - Page 237
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123038/m30627fjpgp_u7c_sml.jpg)
M30627FJPGP#U7C
Manufacturer Part Number
M30627FJPGP#U7C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U7CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.5
Table 17.17
NOTES:
i= 0 to 2
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
1. Set the bit 4 and bit 5 in the U0C0 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
2. TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
Register
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 17.17 lists the Registers to Be Used and Settings in IE Mode. Figure 17.33 shows the Bus Collision
Detect Function-Related BitsBus Collision Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR26 and IFSR27 bits in the IFSR2A register to enable the UART0/UART1 bus collision detect
function.
(3)
in the UCON register.
Jan 10, 2006
Special Mode 3 (IE mode)
Registers to Be Used and Settings in IE Mode
0 to 8
0 to 8
OER, FER, PER, SUM Error flag
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH, UiERE
0 to 3, 7
ABSCS
ACSE
SSS
0 to 7
0 to 7
0 to 7
IFSR26, IFSR27
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
(1)
Page 220 of 390
(1),
Bit
Set transmission data
Reception data can be read
Set a bit rate
Set to “110b”
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TXDi pin output mode
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
(2)
Function
17. Serial Interface
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