M30627FJPGP#U7C Renesas Electronics America, M30627FJPGP#U7C Datasheet - Page 80
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123038/m30627fjpgp_u7c_sml.jpg)
M30627FJPGP#U7C
Manufacturer Part Number
M30627FJPGP#U7C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U7CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 8.3
8.2.4
Table 8.3
Table 8.4
8.2.5
16-bit
(BYTE pin input = L)
16-bit
(BYTE pin input = L)
8-bit
(BYTE pin input = H)
A0/D0 to A7/D7
Data Bus Width
Data Bus Width
NOTES :
When BYTE Pin Input = H
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD, BHE
and WR or a combination of RD, WRL and WRH by using the PM02 bit in the PM0 register. When the data
bus is 8 bits wide, use a combination of RD, WR and BHE.
Table 8.3 shows the Operation of RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD, WRL,
and BHE Signals.
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE
signal falls.
1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
A8 to A19
Jan 10, 2006
ALE
Read and Write Signals
ALE Signal
Operation of RD, WRL and WRH Signals
Operation of RD, WRL and BHE Signals
ALE Signal, Address Bus, Data Bus
Address
RD
Page 63 of 390
H
H
H
H
RD
L
L
L
L
H
H
H
L
Address
WRL
H
H
H
H
L
L
L
L
WRL
(1)
H
H
L
L
Not used H or L Write 1 byte of data
Not used H or L Read 1 byte of data
Data
BHE
H
H
L
L
L
L
WRH
H
H
L
L
A0
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
H
H
L
L
L
L
A1/D0 to A8/D7
When BYTE Pin Input = L
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
A9 to A19
ALE
A0
Status of External Data Bus
Status of External Data Bus
Address
Address
Address
Data
8. Bus
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