M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 24
![IC M32C/87 MCU FLASH 100QFP](/photos/12/31/123127/m30879flfp_u3_sml.jpg)
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 1 Overview
1 .
0
(11) Vector Register (VCT)
(12) DMA Mode Registers (DMD0/DMD1)
(13) DMA Transfer Count Registers (DCT0/DCT1)
(14) DMA Transfer Count Reload Registers (DRC0/DRC1)
(15) DMA Memory Address Registers (DMA0/DMA1)
(16) DMA SFR Address Registers (DSA0/DSA1)
(17) DMA Memory Address Reload Registers (DRA0/DRA1)
9
0 .
B
This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is
generated.
These registers consist of 8 bits and are used to set transfer mode, etc. for DMA.
These registers consist of 16 bits and are used to reload the DMA transfer count registers.
These registers consist of 24 bits and are used to set a memory address at the source or destination of
DMA transfer.
These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA
transfer.
These registers consist of 24 bits and are used to reload the DMA memory address registers.
0
These registers consist of 16 bits and are used to set the number of DMA transfers to be performed.
0
3
1
2
9
0
0 -
0
6
1
0 .
0
0
5
3 .
1
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a
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6
f o
3
3
5
1.3 Register Configuration
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