M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 98
![IC M32C/87 MCU FLASH 100QFP](/photos/12/31/123127/m30879flfp_u3_sml.jpg)
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R
R
e
E
DSUB
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
[ Flag Change ]
[ Description Example ]
v
J
Chapter 3
1 .
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM8/#IMM16
Change
Conditions
0
Flag
9
DSUB.size
dest
0 .
B
• This instruction subtracts
• When (.W) is specified for the size specifier (.size) and
S :
Z :
C :
DSUB.B
DSUB.W
DSUB.W
0
0
bits become 0. Also, when
the data to be operated on.
3
1
2
9
0
0 -
U
0
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
The flag is set when the operation resulted in any value equal to or greater than 0; otherwise
cleared.
6
1
0 .
0
dest
0
5
I
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
3 .
Functions
1
src,dest
#3,R0L
R1,R0
[A0],[A1]
O
p
-
a
g
e
B
src
src
80
S
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
f o
src
Z
3
src
3
5
from
Decimal subtract without borrow
D
is the address register, the 16 low-order bits of the address register are
dest
C
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
Decimal SUBtract
in decimal and stores the result in
B , W
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
dest
[ Instruction Code/Number of Cycles ]
is the address register, the 8 high-order
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
dest
dest
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
.
3.2 Functions
DSUB
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
Page= 217
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