MPC555LFCZP40 Freescale Semiconductor, MPC555LFCZP40 Datasheet - Page 5

• Manufacturer Part Number: MPC555LFCZP40
• Description: IC MPU 32BIT 40MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFCZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-PBGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

1.2.10 Two CAN 2.0B Controller Modules (TouCAN)
Each TouCAN provides these features:
1.2.11 Queued Serial Multi-Channel Module (QSMCM)
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Full implementation of CAN protocol specification, version 2.0A and 2.0B
Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
Global mask register for message buffers 0 to 13
Independent mask registers for message buffers 14 and 15
Programmable transmit-first scheme: lowest ID or lowest buffer number
16-bit free-running timer for message time-stamping
Low power sleep mode with programmable wake-up on bus activity
Programmable I/O modes
Maskable interrupts
Independent of the transmission medium (external transceiver is assumed)
Open network architecture
Multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode with programmable wakeup on bus activity
Queued serial peripheral interface (QSPI)
— Provides full-duplex communication port for peripheral expansion or interprocessor
— Up to 32 preprogrammed transfers, reducing overhead
— 160-byte queue buffer
— Programmable transfer length: from 8 to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock divided by 4
— Four programmable peripheral-select pins support up to 16 devices
— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals
Two serial communications interfaces (SCI). Each SCI offers these features:
— UART mode provides NRZ format and half-or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1 only)
— Advanced error detection and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete
communication
(e.g., – serial A/D converters, I/O latches, etc.)
a new address byte is received
inputs, allowing realization of a low-speed serial protocol
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MPC555 Product Brief
Key Features
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