PIC10F220T-I/OT Microchip Technology, PIC10F220T-I/OT Datasheet - Page 23

• Manufacturer Part Number: PIC10F220T-I/OT
• Description: IC PIC MCU FLASH 256X12 SOT23-6
• Manufacturer: Microchip Technology
• Series: PIC® 10Fr

Specifications of PIC10F220T-I/OT

• Program Memory Type: FLASH
• Program Memory Size: 384B (256 x 12)
• Package / Case: SOT-23-6
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: POR, WDT
• Number Of I /o: 3
• Ram Size: 16 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC10F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 16 B
• Interface Type: USB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2-ch x 8-bit
• Package: 6SOT-23
• Device Core: PIC
• Family Name: PIC10
• Maximum Speed: 8 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162070 - HEADER INTRFC MPLAB ICD2 8/14PXLT06SOT - SOCKET TRAN ICE 6SOT W/CABLEAC163020 - ADAPTER PROGRAMMER PIC10F2XXAC164320 - MODULE SKT MPLAB PM3 80TQFPAC164037 - MODULE SKT 6L PROMATE II SOT23
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: PIC10F220T-I/OTTR

5.0
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not individually pin selectable. If GP3/
MCLR is configured as MCLR, a weak pull-up can be
enabled via the Configuration Word. Configuring GP3
as MCLR disables the wake-up on change function for
this pin.
5.2
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input only, and the GP2/T0CKI/
FOSC4 pin, which may be controlled by various
registers. See Table 5-1.
TABLE 5-1:
TABLE 5-2:
© 2007 Microchip Technology Inc.
FOSC4
T0CS
ANS1
ANS0
MCLRE
Legend:
Note:
Priority
I/O PORT
GPIO
TRIS Registers
1
2
3
Bit
— = Condition of bit will have no effect on the setting of the pin to Digital mode.
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
ORDER OF PRECEDENCE FOR PIN FUNCTIONS
REQUIREMENTS TO MAKE PINS AVAILABLE IN DIGITAL MODE
TRIS GPIO
GP0
AN0
—
GP0
—
—
—
—
0
TRIS GPIO
GP1
AN1
—
GP1
—
—
—
—
0
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
5.3
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3, which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1:
Note 1: I/O pins have protection diodes to V
TRIS ‘f’
Data
Bus
WR
Port
W
Reg
2: See Table 3-1 for buffer type.
I/O Interfacing
D
D
V
SS
CK
CK
TRIS
Latch
Data
Latch
PIC10F220/222
Reset
.
TRIS GPIO
GP2
—
—
—
FOSC4
0
0
T0CKI
GP2
Q
Q
Q
Q
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
RD Port
(2)
V
V
P
N
SS
DD
DS41270E-page 21
V
V
GP3
DD
SS
—
—
—
—
0
MCLR
(1)
GP3
—
—
DD
I/O
pin
and