ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 3
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ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
2. Overview
8127D–AVR–02/10
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer
to optimize power consumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 16 general purpose working registers and
system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock cycle.
The resulting architecture is compact and code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
PROGRAMMING
INSTRUCTION
INSTRUCTION
INTERFACE
PROGRAM
REGISTER
DECODER
CONTROL
DATA REGISTER
FLASH
LOGIC
LINES
ISP
PORT B
Block Diagram
V
DRIVERS
PORT B
CC
PB3:0
REG. PORT B
REGISTERS
DIRECTION
PROGRAM
REGISTER
COUNTER
PURPOSE
GENERAL
POINTER
STATUS
STACK
SRAM
ALU
X
Y
Z
GND
8-BIT DATA BUS
COMPARATOR
MCU STATUS
OSCILLATOR
RESET FLAG
WATCHDOG
INTERRUPT
COUNTER0
REGISTER
REGISTER
INTERNAL
ANALOG
TIMER/
TIMER
UNIT
ATtiny4/5/9/10
RESET
OSCILLATOR
CALIBRATED
TIMING AND
CONTROL
ADC
3