ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 51

• Manufacturer Part Number: ATTINY5-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY5x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

10.4
10.4.1
10.4.2
8127D–AVR–02/10
Register Description
PORTCR – Port Control Register
PUEB – Port B Pull-up Enable Control Register
Table 10-5.
Notes:
• Bits 7:2, 0 – Reserved
These bits are reserved and will always read zero.
• Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The interme-
diate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see
Bit
0x03
Read/Write
Initial Value
Bit
0x03
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. EXT_CLOCK is 1 when external clock is selected as main clock.
Overriding Signals for Alternate Functions in PB1..PB0
PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1
EXT_CLOCK
0
EXT_CLOCK
0
EXT_CLOCK
EXT_CLOCK
0
EXT_CLOCK
ADC1D
(EXT_CLOCK
(EXT_CLOCK
CLOCK/ICP0/PCINT1 Input
ADC1/Analog Comparator Negative Input
R
7
–
0
R
7
–
0
“Break-Before-Make Switching” on page
R
R
6
–
0
6
–
0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
+ OC0B Enable
• OC0B
+ (PCINT1 • PCIE0) +
• PWR_DOWN) +
• PCINT1 • PCIE0)
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
PUEB3
R/W
3
0
R
3
–
0
43.
PB0/ADC0/AIN0/OC0A/PCINT0
0
0
0
0
OC0A Enable
OC0A
0
(PCINT0 • PCIE0) + ADC0D
PCINT0 • PCIE0
PCINT0 Input
ADC0/Analog Comparator Positive Input
PUEB2
R/W
2
0
R
2
–
0
ATtiny4/5/9/10
PUEB1
BBMB
R/W
R/W
1
0
1
0
PUEB0
R/W
R
0
0
0
–
0
PORTCR
PUEB
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