ATTINY5-TSHR Atmel, ATTINY5-TSHR Datasheet - Page 56
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATTINY5-TSHR
Manufacturer Part Number
ATTINY5-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY5-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY5x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATTINY5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
11.3.2
11.4
56
Counter Unit
ATtiny4/5/9/10
External Clock Source
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
a functional equivalent block diagram of the T0 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
6) edge it detects.
Figure 11-3. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 11-4 on page 57
Tn
clk
I/O
D
LE
Q
ExtClk
shows a block diagram of the counter and its surroundings.
Synchronization
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CS2:0 = 7) or negative (CS2:0 =
D
Figure 11-3 on page 56
Q
clk
I/O
Edge Detector
). The latch is trans-
clk_I/O
8127D–AVR–02/10
/2.5.
Tn_sync
(To Clock
Select Logic)
Tn
shows
). The