ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 16
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ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
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5.3
I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in
“Register Summary” on page
150.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed using the LD and ST instructions, enabling data transfer between the 16 general pur-
pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin-
gle bits can be checked by using the SBIS and SBIC instructions. See document “AVR
Instruction Set” and section
“Instruction Set Summary” on page 152
for more details. When
using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such status flags. The CBI and SBI instructions work on registers in the address range 0x00
to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
ATtiny4/5/9/10
16
8127D–AVR–02/10
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