ATTINY20-SSU Atmel, ATTINY20-SSU Datasheet - Page 131
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ATTINY20-SSU
Manufacturer Part Number
ATTINY20-SSU
Description
MCU AVR 2KB FLASH 12MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-SSU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8235B–AVR–04/11
Low periods: Longer than 2 CPU clock cycles.
High periods: Longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to
“Alternate Port Functions” on page
Table 16-1.
Note:
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI
with DDB5 and DDR_SPI with DDRB.
Assembly Code Example
MOSI
MISO
SCK
SPI_MasterInit:
SPI_MasterTransmit:
Wait_Transmit:
Pin
SS
; Set MOSI and SCK output, all others input
ldi
out
; Enable SPI, Master, set clock rate fck/16
ldi
out
ret
; Start transmission of data (r16)
out
; Wait for transmission complete
in
sbrsr16, SPIF
rjmp Wait_Transmit
ret
See
direction of the user defined SPI pins.
“Alternate Functions of Port B” on page 55
Table 16-1 on page
r17,(1<<DD_MOSI)|(1<<DD_SCK)
DDR_SPI,r17
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
SPCR,r17
SPDR,r16
r16, SPSR
SPI Pin Overrides
Direction, Master SPI
User Defined
Input
User Defined
User Defined
131. For more details on automatic port overrides, refer to
49.
for a detailed description of how to define the
Direction, Slave SPI
Input
User Defined
Input
Input
ATtiny20
131
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