ATTINY20-SSU Atmel, ATTINY20-SSU Datasheet - Page 68
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ATTINY20-SSU
Manufacturer Part Number
ATTINY20-SSU
Description
MCU AVR 2KB FLASH 12MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY20-EK1.pdf
(224 pages)
Specifications of ATTINY20-SSU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, TWI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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11.7.4
68
ATtiny20
Phase Correct PWM Mode
narrow spike for each TOP+1 timer clock cycle. Setting the OCR0x equal to TOP will result in a
constantly high or low output (depending on the polarity of the output set by the COM0x[1:0]
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC0A to toggle its logical level on each Compare Match (COM0A[1:0] = 1). The waveform
generated will have a maximum frequency of f
similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-
TOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5. In non-
inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-
counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the sym-
metric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
Figure 11-7. Phase Correct PWM Mode, Timing Diagram
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
TCNTn
OCnx
OCxn
Period
Figure
11-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
1
2
clk_I/O
/2 when OCR0A is set to zero. This feature is
3
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
8235B–AVR–04/11
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