ATTINY20-MMHR Atmel, ATTINY20-MMHR Datasheet - Page 10

• Manufacturer Part Number: ATTINY20-MMHR
• Description: MCU AVR 2KB FLASH 12MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.5
4.6
10
Stack Pointer
Instruction Execution Timing
ATtiny20
Figure 4-3.
In different addressing modes these address registers function as automatic increment and
automatic decrement (see document “AVR Instruction Set” and section
mary” on page 210
The stack is mainly used for storing temporary data, local variables and return addresses after
interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the
top of the stack. Note that the stack grows from higher memory locations to lower memory loca-
tions. This means that the PUSH instructions decreases and the POP instruction increases the
stack pointer value.
The stack pointer points to the area of data memory where subroutine and interrupt stacks are
located. This stack space must be defined by the program before any subroutine calls are exe-
cuted or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and
incremented by one when data is fetched with the POP instruction. It is decremented by two
when the return address is put on the stack by a subroutine call or a jump to an interrupt service
routine, and incremented by two when data is fetched by a return from subroutine (the RET
instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The
width of the stack pointer and the number of bits implemented is device dependent. In some
AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register
is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the
lowest address of SRAM. See
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
X-register
Y-register
Z-register
The X-, Y-, and Z-registers
for details).
15
7
15
7
15
7
Figure 5-1 on page
CPU
R27
R29
R31
XH
YH
ZH
, directly generated from the selected clock source for the
16.
0
0
0
7
7
7
“Instruction Set Sum-
XL
YL
ZL
R26
R28
R30
8235B–AVR–04/11
0
0
0
0
0
0