ATTINY20-MMHR Atmel, ATTINY20-MMHR Datasheet - Page 156

• Manufacturer Part Number: ATTINY20-MMHR
• Description: MCU AVR 2KB FLASH 12MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3.10
18.4
156
Access Layer of Tiny Programming Interface
ATtiny20
Direction Change
The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver
is always enabled when a logical zero is sent. When sending successive logical ones, the output
is only driven actively during the first clock cycle. After this, the output driver is automatically tri-
stated and the TPIDATA line is kept high by the internal pull-up. The output is re-enabled, when
the next logical zero is sent.
The collision detection is enabled in transmit mode, when the output driver has been disabled.
The data line should now be kept high by the internal pull-up and it is monitored to see, if it is
driven low by the external programmer. If the output is read low, a collision has been detected.
There are some potential pit-falls related to the way collision detection is performed. For exam-
ple, collisions cannot be detected when the TPI physical layer transmits a bit-stream of
successive logical zeros, or bit-stream of alternating logical ones and zeros. This is because the
output driver is active all the time, preventing polling of the TPIDATA line. However, within a sin-
gle frame the two stop bits should always be transmitted as logical ones, enabling collision
detection at least once per frame (as long as the frame format is not violated regarding the stop
bits).
The TPI physical layer will cease transmission when it detects a collision on the TPIDATA line.
The collision is signalized to the TPI access layer, which immediately changes the physical layer
to receive mode and goes to the error state. The TPI access layer can be recovered from the
error state only by sending a BREAK character.
In order to ensure correct timing of the half-duplex operation, a simple guard time mechanism
has been added to the physical layer. When the TPI physical layer changes from receive to
transmit mode, a configurable number of additional IDLE bits are inserted before the start bit is
transmitted. The minimum transition time between receive and transmit mode is two IDLE bits.
The total IDLE time is the specified guard time plus two IDLE bits.
The guard time is configured by dedicated bits in the TPIPCR register. The default guard time
value after the physical layer is initialized is 128 bits.
The external programmer looses control of the TPIDATA line when the TPI target changes from
receive mode to transmit. The guard time feature relaxes this critical phase of the communica-
tion. When the external programmer changes from receive mode to transmit, a minimum of one
IDLE bit should be inserted before the start bit is transmitted.
The TPI access layer is responsible for handling the communication with the external program-
mer. The communication is based on a message format, where each message comprises an
instruction followed by one or more byte-sized operands. The instruction is always sent by the
external programmer but operands are sent either by the external programmer or by the TPI
access layer, depending on the type of instruction issued.
The TPI access layer controls the character transfer direction on the TPI physical layer. It also
handles the recovery from the error state after exception.
The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control
and status registers in the TPI access Layer. The CSS consist of registers directly involved in
the operation of the TPI itself. These register are accessible using the SLDCS and SSTCS
instructions.
8235B–AVR–04/11