ATTINY20-MMHR Atmel, ATTINY20-MMHR Datasheet - Page 72

• Manufacturer Part Number: ATTINY20-MMHR
• Description: MCU AVR 2KB FLASH 12MHZ 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY20-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

72
ATtiny20
Table 11-3.
Note:
Table 11-4
PWM mode.
Table 11-4.
Note:
• Bits 5:4 – COM0B[1:0] : Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of COM0B[1:0] bits
are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to.
The Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to
enable the output driver.
When OC0B is connected to the pin, the function of COM0B[1:0] bits depend on WGM0[2:0] bit
setting.
or CTC mode (non-PWM).
Table 11-5.
COM0A1
COM0A1
COM0B1
0
0
1
1
0
0
1
1
0
0
1
1
Table 11-5
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
1. When OCR0A equals TOP and COM0A1 is set, the Compare Match is ignored, but the set or
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 66
clear is done at TOP. See
shows COM0A[1:0] bit functionality when WGM0[2:0] bits are set to phase correct
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
Compare Output Mode, non-PWM Mode
COM0A0
COM0A0
COM0B0
for more details.
shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to normal
0
1
0
1
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0A disconnected
WGM02 = 0: Normal Port Operation, OC0A Disconnected
WGM02 = 1: Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A at BOTTOM (non-inverting mode)
Set OC0A on Compare Match
Clear OC0A at BOTTOM (inverting mode)
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Description
Normal port operation, OC0B disconnected.
Toggle OC0B on Compare Match
Clear OC0B on Compare Match
Set OC0B on Compare Match
“Phase Correct PWM Mode” on page 68
(1)
(1)
for more details.
“Fast PWM Mode” on
8235B–AVR–04/11