PIC12F609-I/MF Microchip Technology, PIC12F609-I/MF Datasheet - Page 109
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PIC12F609-I/MF
Manufacturer Part Number
PIC12F609-I/MF
Description
IC PIC MCU FLASH 1KX14 8-DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC12F609T-ISN.pdf
(8 pages)
5.PIC12F615-EMF.pdf
(196 pages)
Specifications of PIC12F609-I/MF
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
5
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
2
No. Of Pwm
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC12F609T-ISN PDF datasheet
- PIC12F609T-ISN PDF datasheet #2
- PIC12F609T-ISN PDF datasheet #3
- PIC12F609T-ISN PDF datasheet #4
- PIC12F615-EMF PDF datasheet #5
- Current page: 109 of 196
- Download datasheet (3Mb)
FIGURE 11-8:
TABLE 11-7:
© 2008 Microchip Technology Inc.
INTCON
IOC
PIR1
PIE1
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
INSTRUCTION FLOW
Name
Note 1: PIC12F615/HV615 only.
GIE bit
(INTCON reg.)
INTF flag
(INTCON reg.)
CLKOUT
INT pin
OSC1
Instruction
Executed
Note 1: INTF flag is sampled here (every Q1).
Instruction
Fetched
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
Shaded cells are not used by the interrupt module.
Bit 7
GIE
(3)
—
—
—
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Q1
ADIE
ADIF
PEIE
Bit 6
Inst (PC – 1)
Inst (PC)
—
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(1)
(1)
Q3 Q4
(4)
CCP1IE
CCP1IF
IOC5
Bit 5
T0IE
(5)
(1)
(1)
Q1
Inst (PC + 1)
Inst (PC)
INTE
IOC4
Bit 4
Q2
(1)
—
—
PIC12F609/615/12HV609/615
PC + 1
Q3 Q4
CY
. Synchronous latency = 3 T
CMIE
GPIE
CMIF
IOC3
Bit 3
Interrupt Latency
Q1
IOC2
Bit 2
T0IF
Dummy Cycle
—
—
Q2
PC + 1
—
Q3 Q4
TMR2IE
TMR2IF
Section 15.0 “Electrical Specifications”
IOC1
INTF
Bit 1
(2)
CY
, where T
(1)
(1)
Q1
Dummy Cycle
Inst (0004h)
TMR1IE -00- 0-00 -000 0-00
TMR1IF -00- 0-00 -000 0-00
Q2
GPIF
IOC0
Bit 0
0004h
CY
= instruction cycle time. Latency
Q3 Q4
0000 0000 0000 0000
--00 0000 --00 0000
POR, BOR
Value on
Q1
DS41302B-page 107
.
Inst (0005h)
Q2
Inst (0004h)
0005h
Value on
all other
Q3 Q4
Resets
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