PIC16F630T-I/ST Microchip Technology, PIC16F630T-I/ST Datasheet

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PIC16F630T-I/ST

Manufacturer Part Number
PIC16F630T-I/ST
Description
IC MCU FLASH 1KX14 14TSSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F630T-I/ST

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
PIC16F630/676
Data Sheet
14-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
 2010 Microchip Technology Inc.
DS40039F

Related parts for PIC16F630T-I/ST

PIC16F630T-I/ST Summary of contents

Page 1

... Microchip Technology Inc. PIC16F630/676 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS40039F ...

Page 2

... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Program Memory Device Flash (words) PIC16F630 1024 PIC16F676 1024  2010 Microchip Technology Inc. PIC16F630/676 Low-Power Features: • Standby Current 2.0V, typical • Operating Current: - 8.5  kHz, 2.0V, typical - 100  MHz, 2.0V, typical • Watchdog Timer Current - 300 nA @ 2.0V, typical • ...

Page 4

... PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/AN3/CLKOUT RA3/MCLR/V DS40039F-page RA0/CIN+/ICSPDAT 3 12 RA1/CIN-/ICSPCLK 4 11 RA2/COUT/T0CKI/INT PP RC5 5 RC0 10 RC4 6 RC1 9 RC3 7 RC2 RA0/AN0/CIN+/ICSPDAT 3 12 RA1/AN1/CIN-/ RA2/AN2/COUT/T0CKI/INT RC5 5 10 RC0/AN4 RC4 6 RC1/AN5 9 RC3/AN7 7 RC2/AN6 8 /ICSPCLK REF  2010 Microchip Technology Inc. ...

Page 5

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. PIC16F630/676 DS40039F-page 5 ...

Page 6

... PIC16F630/676 NOTES: DS40039F-page 6  2010 Microchip Technology Inc. ...

Page 7

... V REF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7  2010 Microchip Technology Inc. Sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F630 and PIC16F676 devices are covered by this Data Sheet. They are identical, except the PIC16F676 has a 10-bit A/D converter ...

Page 8

... A/D Channel 5 input. TTL CMOS Bidirectional I/O. AN6 — A/D Channel 6 input. TTL CMOS Bidirectional I/O. AN7 — A/D Channel 7 input. TTL CMOS Bidirectional I/O. TTL CMOS Bidirectional I/O. Power — Ground reference. Power — Positive supply. Description  2010 Microchip Technology Inc. ...

Page 9

... Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory  2010 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Regis- ters and the Special Function Registers. The Special Function Registers are located in the first 32 locations of each bank ...

Page 10

... General Purpose accesses Registers 20h-5Fh 64 Bytes 5Fh 60h 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. 1: Not a physical register. 2: PIC16F676 only.  2010 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah ...

Page 11

... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. 2: IRP and RP1 bits are reserved, always maintain these bits clear. 3: PIC16F676 only.  2010 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 TO ...

Page 12

... ANS1 ANS0 1111 1111 48 — — — — — — --11 -111 22 WPUA1 WPUA0 IOCA1 IOCA0 --00 0000 23 — — — — VR1 VR0 0-0- 0000 44 0000 0000 51 0000 0000 ---- x000 52 ---- ---- 51 xxxx xxxx 46 — — -000 ---- 47,63  2010 Microchip Technology Inc. ...

Page 13

... Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affect- ing any Status bits, see Section 10.0 “ ...

Page 14

... Section 4.4 “Prescaler”. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 15

... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. PIC16F630/676 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 16

... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 U-0 CMIE — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2010 Microchip Technology Inc. U-0 R/W-0 TMR1IE — bit Bit is unknown ...

Page 17

... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. PIC16F630/676 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 18

... CAL3 CAL2 CAL1 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-0 R/W-x — POR BOD bit Bit is unknown R/W-0 U-0 U-0 CAL0 — — bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 19

... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556).  2010 Microchip Technology Inc. PIC16F630/676 2.3.2 STACK The PIC16F630/676 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1) ...

Page 20

... Not Used Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing ( FSR Register Location Select 1FFh  2010 Microchip Technology Inc. ...

Page 21

... Port pin is > Port pin is <V Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Note: The ANSEL (91h) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input ...

Page 22

... Q2 cycle), then the RAIF interrupt flag may not get set. R/W-x R/W-x R/W-x TRISA2 TRISA1 TRISA0 bit Bit is unknown R/W-1 R/W-1 R/W-1 WPUA2 WPUA1 WPUA0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 23

... IOCA<5:0>: Interrupt-on-Change PORTA Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. U-0 R/W-0 R/W-0 R/W-0 — IOCA5 IOCA4 IOCA3 W = Writable bit U = Unimplemented bit, read as ‘ ...

Page 24

... FIGURE 3-1: BLOCK DIAGRAM OF RA0 AND RA1 PINS Analog Input Mode Data Bus WPUA RAPU RD WPUA PORTA TRISA Analog Input Mode RD TRISA RD PORTA IOCA EN RD IOCA Interrupt-on-Change RD PORTA To Comparator To A/D Converter  2010 Microchip Technology Inc Weak V DD I/O pin V SS ...

Page 25

... Q EN Interrupt-on-Change RD PORTA To TMR0 To INT To A/D Converter  2010 Microchip Technology Inc. 3.2.3.4 Figure 3-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: Data Bus ...

Page 26

... IOCA Interrupt-on-Change To TMR1 or CLKGEN Note 1: Timer1 LP Oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed. BLOCK DIAGRAM OF RA5 INTOSC Mode (1) TMR1LPEN V DD Weak RAPU Oscillator Circuit OSC2 V DD I/O pin V SS INTOSC Mode ( PORTA  2010 Microchip Technology Inc. ...

Page 27

... ANS6 95h WPUA — — 96h IOCA — — Note 1: PIC16F676 only. Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.  2010 Microchip Technology Inc. PIC16F630/676 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 ...

Page 28

... RC4 AND RC5 The RC4 and RC5 pins are configurable to function as a general purpose I/Os. FIGURE 3-7: Data bus PORTC TRISC RD TRISC RD PORTC V DD I/O Pin V SS BLOCK DIAGRAM OF RC4 AND RC5 PINS V DD I/O Pin V SS  2010 Microchip Technology Inc. ...

Page 29

... TRISC — — (1) ANS7 ANS6 91h ANSEL Note 1: PIC16F676 only. Legend unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC unknow  2010 Microchip Technology Inc. U-0 R/W-x R/W-x R/W-x RC5 RC4 RC3 — Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 30

... PIC16F630/676 NOTES: DS40039F-page 30  2010 Microchip Technology Inc. ...

Page 31

... Watchdog Timer WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.  2010 Microchip Technology Inc. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin RA2/T0CKI. The incrementing edge is determined ...

Page 32

... PIC16F676. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared OSC ’. 0 R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 33

... OPTION_REG RAPU INTEDG 85h TRISA — — Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module.  2010 Microchip Technology Inc. PIC16F630/676 EXAMPLE 4-1: BCF STATUS,RP0 CLRWDT CLRF TMR0 BSF STATUS,RP0 MOVLW b’ ...

Page 34

... Timer1 module. Note: Additional information on timer modules is available in the PIC ence Manual, (DS33023). 0 TMR1L 1 T1SYNC 1 Prescaler OSC Internal 0 Clock 2 T1CKPS<1:0> TMR1CS ® Mid-Range Refer- TMR1ON TMR1GE T1G TMR1ON TMR1GE Synchronized Clock Input Synchronize Detect Sleep Input  2010 Microchip Technology Inc. ...

Page 35

... Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010 Microchip Technology Inc. 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...

Page 36

... Stops Timer1 Legend Readable bit - n = Value at POR DS40039F-page 36 R/W-0 R/W-0 R/W-0 : /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 37

... PIE1 EEIE ADIE Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2010 Microchip Technology Inc. 5.5 Timer1 Oscillator A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscilla- tor is a low power oscillator rated kHz ...

Page 38

... PIC16F630/676 NOTES: DS40039F-page 38  2010 Microchip Technology Inc. ...

Page 39

... Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. Voltage Reference that can also be applied to an input of the comparator. In addition, RA2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator ...

Page 40

... Table 6-1. DS40039F-page 40 TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions + is less > < > < FIGURE 6- Output Note: CINV bit (CMCON<4>) is clear. CINV COUT SINGLE COMPARATOR + Output –  2010 Microchip Technology Inc. ...

Page 41

... RA2/COUT Analog Input, ports always reads ‘0’ Digital Input CIS = Comparator Input Switch (CMCON<3>)  2010 Microchip Technology Inc. level may not be valid for a specified period of time. Refer to the specifications in Section 12.0 “Electri- cal Specifications”. Note: Comparator interrupts should be disabled during a Comparator mode change ...

Page 42

... TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified CINV CMCON EN Reset impedance of 10 k RA0/CIN+ RA1/CIN- CV REF CM2:CM0  2010 Microchip Technology Inc. ...

Page 43

... To minimize power consumption while in Sleep mode, turn off the comparator, CM2:CM0 = 111, and voltage refer- ence, VRCON<7>  2010 Microchip Technology Inc. PIC16F630/676 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range): CV ...

Page 44

... Value on Bit 1 Bit 0 all other POR, BOD Resets INTF RAIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 CM1 CM0 -0-0 0000 -0-0 0000 — TMR1IE 00-- 0--0 00-- 0--0 VR1 VR0 0-0- 0000 0-0- 0000  2010 Microchip Technology Inc. ...

Page 45

... The CHS2:CHS0 (ADCON0<4:2>) control which channel is connected to the sample and hold circuit.  2010 Microchip Technology Inc. circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference ...

Page 46

... ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0  2010 Microchip Technology Inc. ...

Page 47

... OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0: Unimplemented: Read as ‘0’ Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. PIC16F630/676 U-0 R/W-0 R/W-0 R/W-0 — CHS2 CHS1 CHS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...

Page 48

... Legend Readable bit - n = Value at POR DS40039F-page 48 R/W-1 R/W-1 R/W-1 ANS5 ANS4 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 49

... SS = sampling switch C = sample/hold capacitance (from DAC) HOLD  2010 Microchip Technology Inc. is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 7-1 may be used ...

Page 50

... GO ADON 00-0 0000 00-0 0000 TRISA1 TRISA0 --11 1111 --11 1111 TRISC1 TRISC0 --11 1111 --11 1111 — TMR1IE 00-- 0--0 00-- 0--0 ANS1 ANS0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu — — -000 ---- -000 ----  2010 Microchip Technology Inc. ...

Page 51

... EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend Readable bit - n = Value at POR  2010 Microchip Technology Inc. PIC16F630/676 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...

Page 52

... EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown  2010 Microchip Technology Inc. ...

Page 53

... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.  2010 Microchip Technology Inc. PIC16F630/676 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...

Page 54

... Bit 4 Bit 3 Bit 2 — — CMIF — — — WRERR WREN Value on all Value on Bit 1 Bit 0 other POR, BOD Resets — TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ----  2010 Microchip Technology Inc. ...

Page 55

... Watchdog Timer (WDT) • Sleep • Code protection • ID Locations • In-Circuit Serial Programming™  2010 Microchip Technology Inc. PIC16F630/676 The PIC16F630/676 has a Watchdog Timer that is controlled by Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up ...

Page 56

... Specification for more information. R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 (1) (2) (4) ( Writable bit U = Unimplemented bit, read as ‘0’ bit is set 0 = bit is cleared R/P-1 R/P-1 R/P-1 R/P-1 bit bit is unknown  2010 Microchip Technology Inc. ...

Page 57

... A series resistor may be required for AT strip cut crystals varies with the Oscillator mode selected (Approx. value = 10 M  2010 Microchip Technology Inc. FIGURE 9-2: Clock from External System Open Note 1: Functions as RA4 in EC Osc mode. TABLE 9-1: ® ...

Page 58

... OSCILLATOR Z /4. OSC Calibrating the Internal Oscillator CALIBRATING THE INTERNAL OSCILLATOR STATUS, RP0 ;Bank 1 3FFh ;Get the cal value OSCCAL ;Calibrate STATUS, RP0 ;Bank 0 /4) is output on the OSC /4 can be used for test OSC  2010 Microchip Technology Inc. DD ...

Page 59

... Ripple Counter RC OSC Note 1: This is a separate oscillator from the INTOSC/EC oscillator.  2010 Microchip Technology Inc. PIC16F630/676 They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 9-4 ...

Page 60

... OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep reaches DD Detect to DD  2010 Microchip Technology Inc. ...

Page 61

... Figure 9-8). This is useful for testing purposes or to synchronize more than one PIC16F630/676 device operating in parallel. Table 9-6 shows the Reset conditions for some special registers, while Table 9-7 shows the Reset conditions for all the registers.  2010 Microchip Technology Inc. PIC16F630/676 On any Reset (Power-on, Watchdog, etc ...

Page 62

... uuu1 0uuu Wake-up from Sleep PWRTE = 1 1024•T 1024•T OSC OSC — — Value on all Value on Bit 0 other POR, BOD (1) Resets C 0001 1xxx 000q quuu BOD ---- --0x ---- --uq PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu  2010 Microchip Technology Inc. ...

Page 63

... If wake-up was due to data EEPROM write completing, bit A/D conversion completing, bit Comparator input changing, bit Timer1 rolling over, bit All other interrupts generating a wake-up will cause these bits Reset was due to brown-out, then bit All other Resets will cause bit  2010 Microchip Technology Inc. • MCLR Reset • WDT Reset (1) • ...

Page 64

... MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS40039F-page 64 T PWRT T OST T PWRT T OST DD T PWRT T OST  2010 Microchip Technology Inc. ): CASE CASE ...

Page 65

... Figure 9-11). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be  2010 Microchip Technology Inc. determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests ...

Page 66

... IOCA-RA1 IOCA1 IOCA-RA2 IOCA2 IOCA-RA3 IOCA3 IOCA-RA4 IOCA4 IOCA-RA5 IOCA5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC16F676 only. DS40039F-page 66 T0IF Wake-up (If in Sleep mode) T0IE INTF INTE RAIF RAIE PEIE GIE  2010 Microchip Technology Inc. Interrupt to CPU ...

Page 67

... Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2010 Microchip Technology Inc. 9.4.3 PORTA INTERRUPT An input change on PORTA change sets the RAIF (INTCON< ...

Page 68

... Max. WDT prescaler) it may take several seconds before a WDT time-out occurs. Value on all Value on Bit 0 other POR, BOD Resets RAIF 0000 0000 0000 000u TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0 instructions clear the WDT SLEEP = Min., Temperature = Max., DD  2010 Microchip Technology Inc. ...

Page 69

... SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 81h OPTION_REG RAPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer.  2010 Microchip Technology Inc. PIC16F630/676 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA ...

Page 70

... OST Interrupt Latency (Note 3) Processor in Sleep PC+2 PC Inst( Inst( Dummy cycle instruction is being executed, the instruction. If the GIE bit is SLEEP is not desirable, the user SLEEP after the instruction. SLEEP 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h)  2010 Microchip Technology Inc. ...

Page 71

... For complete details of serial programming, please refer to the PIC16F630/676 Programming Specification. A typical In-Circuit Serial Programming connection is shown in Figure 9-14.  2010 Microchip Technology Inc. PIC16F630/676 FIGURE 9-14: not been External ...

Page 72

... PIC16F630/676 NOTES: DS40039F-page 72  2010 Microchip Technology Inc. ...

Page 73

... A read operation is performed on a register even if the instruction writes to that register.  2010 Microchip Technology Inc. For example, a CLRF PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended result of clearing the condition that set the RAIF flag ...

Page 74

... Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk 1010 kkkk kkkk Z ® Mid-Range MCU Family  2010 Microchip Technology Inc. ...

Page 75

... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2010 Microchip Technology Inc. PIC16F630/676 BCF Bit Clear f Syntax: [label] BCF f,b 0  f  127 Operands: 0  ...

Page 76

... Syntax: [label] DECF f,d 0  f  127 Operands: d  [0,1] (  (destination) Operation: Status Affected: Z Description: Decrement register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2010 Microchip Technology Inc. ...

Page 77

... Z Description: The contents of register ‘f’ are incremented. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’.  2010 Microchip Technology Inc. PIC16F630/676 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d 0  f  127 Operands: d  ...

Page 78

... Return with Literal label ] RETLW k 0  k  255 k  (W); TOS  PC None The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.  2010 Microchip Technology Inc. ...

Page 79

... Carry Flag. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’. C Register f  2010 Microchip Technology Inc. PIC16F630/676 SLEEP Syntax: [ label ] SLEEP Operands: None 00h  WDT, Operation: 0  ...

Page 80

... Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2010 Microchip Technology Inc. f,d ...

Page 81

... PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits  2010 Microchip Technology Inc. 11.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 82

... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility  2010 Microchip Technology Inc. ...

Page 83

... Microchip Technology Inc. 11.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip’s most cost effective high-speed hardware ...

Page 84

... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ®  2010 Microchip Technology Inc. ...

Page 85

... SS Thus, a series resistor of 50-100 pulling this pin directly to V  2010 Microchip Technology Inc. ........................................................................... -0. ) ) ...

Page 86

... FIGURE 12-2: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C  T  +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS40039F-page Frequency (MHz Frequency (MHz  2010 Microchip Technology Inc. ...

Page 87

... FIGURE 12-3: PIC16F676 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C  T  +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency.  2010 Microchip Technology Inc. PIC16F630/676 Frequency (MHz) 20 DS40039F-page 87 ...

Page 88

... See section on Power-on Reset for details SS 0.05* — — V/ms See section on Power-on Reset for details — 2.1 — V can be lowered in Sleep mode without losing RAM data. DD  +85°C for industrial A  +125°C for extended A Conditions < MHz: < F < MHz Z OSC  2010 Microchip Technology Inc. ...

Page 89

... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40C  T ...

Page 90

... I and the additional current consumed when this DD PD Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current  2010 Microchip Technology Inc. ...

Page 91

... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40C  T ...

Page 92

... I and the additional current consumed when this DD PD  +125C for extended Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current  2010 Microchip Technology Inc. ...

Page 93

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  T -40° ...

Page 94

... OSC1 pF +85°C A +125° Using EECON to read/write V = Minimum operating MIN voltage ms are violated +85°C A +85°C A +125° Minimum operating MIN voltage V ms are violated  2010 Microchip Technology Inc. ...

Page 95

... MCLR Uppercase letters and their meanings Fall H High I Invalid (High-impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin Legend 464 for all pins for OSC2 output  2010 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid ...

Page 96

... INTOSC mode ns RC Osc mode ns XT Osc mode ns HS Osc mode 4/F CY OSC s LP oscillator, T L/H duty cycle OSC ns HS oscillator, T L/H duty cycle OSC ns XT oscillator, T L/H duty cycle OSC ns LP oscillator ns XT oscillator ns HS oscillator  2010 Microchip Technology Inc. ...

Page 97

... Sleep start-up time These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. PIC16F630/676 Freq Min Typ† Max ...

Page 98

... T — CY OSC New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns —  2010 Microchip Technology Inc. ...

Page 99

... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in Configuration Word is programmed to ‘0’.  2010 Microchip Technology Inc. PIC16F630/676 (Device not in Brown-out Detect time-out 34 DS40039F-page 99 ...

Page 100

... TBD ms Extended Temperature s — — 2.0 2.025 — 2.175 V TBD — — — s 100* — —  2010 Microchip Technology Inc. Conditions = 5V, -40°C to +85°C = 5V, -40°C to +85°C = OSC1 period = 5V, -40°C to +85°C  B (D005) VDD ...

Page 101

... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc ...

Page 102

... LSb DD — V /32 — LSb DD  1/2* — — LSb 1/2* — — LSb — 2k* — — — 10* Comments V Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)  s  2010 Microchip Technology Inc. ...

Page 103

... Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module current is from External V REF 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.  2010 Microchip Technology Inc. Min Typ† Max Units — ...

Page 104

... LSb (i.e., 4 4.096V) from the last sampled volt- age (as stored HOLD If the A/D clock source is selected as RC, a time added before CY the A/D clock starts. This allows the SLEEP instruction to be executed.  2010 Microchip Technology Inc. ...

Page 105

... Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Table 7-1 for minimum conditions.  2010 Microchip Technology Inc. ( 131 ...

Page 106

... PIC16F630/676 NOTES: DS40039F-page 106  2010 Microchip Technology Inc. ...

Page 107

... FIGURE 13-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5  2010 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline ...

Page 108

... DS40039F-page 108 OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD 125 5.0 5.5 - 5.5  2010 Microchip Technology Inc. ...

Page 109

... FIGURE 13-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5  2010 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline ...

Page 110

... DS40039F-page 110 OVER TEMP (-40°C TO +125°C) DD Typical BOD 4 (V) DD OVER TEMP (-40°C TO +125°C) DD Typical Comparator I PD 3.0 3.5 4.0 4.5 V ( 125 5.5 - 125 5.0 5.5  2010 Microchip Technology Inc. ...

Page 111

... FIGURE 13-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5  2010 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A/D I ...

Page 112

... KHZ, C1 AND C2=50 pF) 1.20E-05 1.00E-05 8.00E-06 6.00E-06 4.00E-06 2.00E-06 0.00E+00 2.0 2.5 DS40039F-page 112 OVER TEMP (+125°C) DD Typical A 3 (V) DD OVER TEMP (-40°C TO +125°C), DD Typical 3.0 3.5 4.0 4.5 V (V) DD 125 5.5 - 125 5.0 5.5  2010 Microchip Technology Inc. ...

Page 113

... FIGURE 13-14: TYPICAL 2.5  2010 Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT ...

Page 114

... DS40039F-page 114 = 3.5V) DD Internal Oscillator Frequency vs Temperature 0°C 25°C 85°C Temperature (°C) Internal Oscillator Frequency 3.0V 3.5V 4.0V 4.5V V (V) DD -3sigma average +3sigma 125°C WITH 0.1  F AND 0.01  -3sigma average +3sigma 5.0V 5.5V  2010 Microchip Technology Inc. ...

Page 115

... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5  2010 Microchip Technology Inc. (-40  +125  WDT Time-out 3 3.5 4 4.5 V (V) DD PIC16F630/676 - 125 5 5.5 DS40039F-page 115 ...

Page 116

... PIC16F630/676 NOTES: DS40039F-page 116  2010 Microchip Technology Inc. ...

Page 117

... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. PIC16F630/676 Example 16F630-I e ...

Page 118

... PIC16F630/676 14.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q/LQH 3 ±  PLO %RG\ >3',3@ 1RWH N NOTE 1RWHV DS40039F-page 118  2010 Microchip Technology Inc. ...

Page 119

... PP %RG\ >62,&@ 1RWH N NOTE 1RWHV  2010 Microchip Technology Inc. PIC16F630/676 φ α c β DS40039F-page 119 ...

Page 120

... PIC16F630/676 1RWH DS40039F-page 120  2010 Microchip Technology Inc. ...

Page 121

... PP %RG\ >76623@ 1RWH NOTE 1RWHV  2010 Microchip Technology Inc. PIC16F630/676 φ L DS40039F-page 121 ...

Page 122

... PIC16F630/676 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40039F-page 122  2010 Microchip Technology Inc. ...

Page 123

... Revision E (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section. Revision F (05/2010) Replaced Package Drawings (Rev. BD); Replaced Development Support Section.  2010 Microchip Technology Inc. PIC16F630/676 APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F630/676 devices listed in this data sheet are shown in Table B-1. ...

Page 124

... These differences may cause this device to perform differently in your application than the earlier version of this device.  2010 Microchip Technology Inc. ® PIC16F6XX 20 MHz 1024 bytes 10-bit 64 bytes ...

Page 125

... Code Protection .................................................................. 71 Comparator ......................................................................... 39 Associated Registers .................................................. 44 Configuration............................................................... 41 Effects of a Reset........................................................ 43 I/O Operating Modes................................................... 41 Interrupts..................................................................... 44 Operation .................................................................... 40 Operation During Sleep .............................................. 43  2010 Microchip Technology Inc. PIC16F630/676 Output......................................................................... 42 Reference ................................................................... 43 Response Time .......................................................... 43 Comparator Specifications................................................ 102 Comparator Voltage Reference Specifications................. 102 Configuration Bits ............................................................... 56 Configuring the Voltage Reference..................................... 43 Crystal Operation ...

Page 126

... Interrupt ...................................................................... 35 Modes of Operations .................................................. 35 Operation During SLEEP............................................ 37 Oscillator..................................................................... 37 Prescaler .................................................................... 35 Timer1 Module with Gate Control ....................................... 34 Timing Diagrams CLKOUT and I/O ........................................................ 98 External Clock............................................................. 96 INT Pin Interrupt ......................................................... 67 PIC16F675 A/D Conversion (Normal Mode) ............ 104 PIC16F675 A/D Conversion Timing (Sleep Mode) ... 105  2010 Microchip Technology Inc. ...

Page 127

... DD Timer0 and Timer1 External Clock ........................... 101 Timer1 Incrementing Edge.......................................... 35 Timing Parameter Symbology............................................. 95 TRISIO Registers................................................................ 21 V Voltage Reference Accuracy/Error ..................................... 43 W Watchdog Timer Summary of Registers ................................................ 69 Watchdog Timer (WDT) ...................................................... 68 WWW Address.................................................................. 129 WWW, On-Line Support ....................................................... 5  2010 Microchip Technology Inc. PIC16F630/676 DS40039F-page 127 ...

Page 128

... PIC16F630/676 NOTES: DS40039F-page 128  2010 Microchip Technology Inc. ...

Page 129

... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...

Page 130

... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40039F-page 130 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS40039F  2010 Microchip Technology Inc. ...

Page 131

... TSSOP(4.4 mm) Pattern: 3-Digit Pattern Code for QTP (blank otherwise Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.  2010 Microchip Technology Inc. PIC16F630/676 XXX Examples: Pattern a) PIC16F630 – E/P 301 = Extended Temp., PDIP ...

Page 132

... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350  2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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