PIC16F630T-I/ST Microchip Technology, PIC16F630T-I/ST Datasheet - Page 44

• Manufacturer Part Number: PIC16F630T-I/ST
• Description: IC MCU FLASH 1KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F630T-I/ST

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -

PIC16F630/676
REGISTER 6-2:
6.9
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
TABLE 6-2:
DS40039F-page 44
0Bh/8Bh
0Ch
19h
8Ch
85h
99h
Legend:
Address
CMIE
Comparator Interrupts
bit 7
bit 6
bit 5
bit 4
bit 3-0
INTCON
PIR1
CMCON
PIE1
TRISA
VRCON
Name
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
bit
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
(PIE1<3>)
VREN
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
Bit 7
EEIF
EEIE
bit 7
GIE
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as ‘0’
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as ‘0’
VR3:VR0: CV
When VRR = 1: CV
When VRR = 0: CV
Legend:
R = Readable bit
- n = Value at POR
—
—
R/W-0
VREN
REF
REF
COUT
PEIE
ADIE
Bit 6
ADIF
and
REF
—
—
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
Enable bit
U-0
the
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
Bit 5
T0IE
VRR
value selection bits 0  VR [3:0]  15
—
—
—
REF
REF
PEIE
= (VR3:VR0 / 24) * V
= V
R/W-0
CINV
Bit 4
INTE
VRR
DD
—
—
—
W = Writable bit
‘1’ = Bit is set
bit
/4 + (VR3:VR0 / 32) * V
CMIE
CMIF
RAIE
Bit 3
VR3
CIS
R/W-0
DD
—
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
drain
Note:
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
Bit 2
CM2
T0IF
DD
VR2
—
—
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
VR3
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
DD
INTF
Bit 1
CM1
VR1
—
—
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
R/W-0
VR2
RAIF
Bit 0
CM0
VR0
 2010 Microchip Technology Inc.
0000 0000 0000 000u
-0-0 0000 -0-0 0000
0-0- 0000 0-0- 0000
POR, BOD
Value on
x = Bit is unknown
R/W-0
VR1
Value on
all other
Resets
R/W-0
VR0
bit 0