ATTINY2313V-10SUR Atmel, ATTINY2313V-10SUR Datasheet - Page 98
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ATTINY2313V-10SUR
Manufacturer Part Number
ATTINY2313V-10SUR
Description
MCU AVR 2KB FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY2313-20MU.pdf
(226 pages)
Specifications of ATTINY2313V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
10MHz
Interface Type
SPI/USART/USI
Total Internal Ram Size
128Byte
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
SOIC W
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Compliant
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Phase Correct PWM
Mode
98
ATtiny2313
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-
tion in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x inter-
rupt flag will be set when a compare match occurs.
Figure 47. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag is set accord-
ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer
TCNTn
OCnx
OCnx
Period
1
R
PCPWM
2
=
log
---------------------------------- -
(
log
TOP
3
2 ( )
+
1
)
4
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
Figure
(COMnx1:0 = 2)
(COMnx1:0 = 3)
47. The figure
2543L–AVR–08/10
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