ATTINY2313V-10MUR Atmel, ATTINY2313V-10MUR Datasheet - Page 148
![MCU AVR 2KB FLASH 10MHZ 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY2313V-10MUR
Manufacturer Part Number
ATTINY2313V-10MUR
Description
MCU AVR 2KB FLASH 10MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313V-10MUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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ATtiny2313
• Bit 3..2 – USICS1..0: Clock Source Select
These bits set the clock source for the Shift Register and counter. The data output latch ensures
that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when
using external clock source (USCK/SCL). When software strobe or Timer0 overflow clock option
is selected, the output latch is transparent and therefore the output is changed immediately.
Clearing the USICS1..0 bits enables software strobe option. When using this option, writing a
one to the USICLK bit clocks both the Shift Register and the counter. For external clock source
(USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clock-
ing and software clocking by the USITC strobe bit.
Table 61
used for the Shift Register and the 4-bit counter.
Table 61. Relations between the USICS1..0 and USICLK Setting
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the Shift Register to shift one step and the counter to
increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software
clock strobe option is selected. The output will change immediately when the clock strobe is exe-
cuted, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the
previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed from
a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the
USITC strobe bit as clock source for the 4-bit counter (see
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value is
to be shown on the pin the DDB7 must be set as output (to one). This feature allows easy clock
generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-
ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of
when the transfer is done when operating as a master device.
USICS1
0
0
0
1
1
1
1
shows the relationship between the USICS1..0 and USICLK setting and clock source
USICS0
0
0
1
0
1
0
1
USICLK
X
0
1
0
0
1
1
Shift Register Clock
Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 overflow
External, positive edge
External, negative edge
External, positive edge
External, negative edge
Table
4-bit Counter Clock
Source
No Clock
Software clock strobe
(USICLK)
Timer/Counter0 overflow
External, both edges
External, both edges
Software clock strobe
(USITC)
Software clock strobe
(USITC)
61).
2543L–AVR–08/10
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