ATMEGA48A-MMH Atmel, ATMEGA48A-MMH Datasheet - Page 6
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ATMEGA48A-MMH
Manufacturer Part Number
ATMEGA48A-MMH
Description
IC MCU AVR 4K FLASH 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48A-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.2
8271CS–AVR–08/10
Comparison Between Processors
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P provides the following features:
4K/8K bytes of In-System Programmable Flash with Read-While-Write capabilities,
256/512/512/1K bytes EEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32
general purpose working registers, three flexible Timer/Counters with compare modes, internal
and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface,
an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a pro-
grammable Watchdog Timer with internal Oscillator, and five software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire
Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com-
bined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded con-
trol applications.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P AVR is supported with a full suite of
program and system development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P differ only in memory sizes, boot
loader support, and interrupt vector sizes.
rupt vector sizes for the devices.
Table 2-1.
Device
ATmega48A
ATmega48PA
ATmega88A
ATmega88PA
ATmega168A
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Memory Size Summary
Flash
4K Bytes
4K Bytes
8K Bytes
8K Bytes
16K Bytes
EEPROM
256 Bytes
256 Bytes
512 Bytes
512 Bytes
512 Bytes
Table 2-1
RAM
512 Bytes
512 Bytes
1K Bytes
1K Bytes
1K Bytes
summarizes the different memory and inter-
2 instruction words/vector
Interrupt Vector Size
1 instruction word/vector
1 instruction word/vector
1 instruction word/vector
1 instruction word/vector
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