ATMEGA48-20PU Atmel, ATMEGA48-20PU Datasheet

IC AVR MCU 4K 20MHZ 5V 28DIP

ATMEGA48-20PU

Manufacturer Part Number
ATMEGA48-20PU
Description
IC AVR MCU 4K 20MHZ 5V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48-20PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USART/Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
512Byte
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA48-20PU
Manufacturer:
ATMEL
Quantity:
42
Part Number:
ATMEGA48-20PU
Manufacturer:
ATMEL
Quantity:
328
Features
Note:
High Performance, Low Power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Temperature Range:
Speed Grade:
Low Power Consumption
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
– 4/8/16 Kbytes of In-System Self-programmable Flash program memory
– 256/512/512 Bytes EEPROM
– 512/1K/1K Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
– 6-channel 10-bit ADC in PDIP Package
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– DebugWIRE On-Chip Debug System
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
– 1.8V - 5.5V for ATmega48V/88V/168V
– 2.7V - 5.5V for ATmega48/88/168
– -40
– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V
– ATmega48/88/168: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V
– Active Mode:
– Power-down Mode:
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
250 µA at 1 MHz, 1.8V
15 µA at 32 kHz, 1.8V (including Oscillator)
0.1 µA at 1.8V
1. See
°
C to 85
“Data Retention” on page 7
°
C
®
AVR
for details.
®
8-Bit Microcontroller
2
C compatible)
()
8-bit
Microcontroller
with 4/8/16K
Bytes In-System
Programmable
Flash
ATmega48/V
ATmega88/V
ATmega168/V
Rev. 2545S–AVR–07/10

Related parts for ATMEGA48-20PU

ATMEGA48-20PU Summary of contents

Page 1

... • Speed Grade: – ATmega48V/88V/168V MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega48/88/168 MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Low Power Consumption – Active Mode: 250 µ MHz, 1.8V 15 µ kHz, 1.8V (including Oscillator) – Power-down Mode: 0.1 µA at 1.8V Note: 1 ...

Page 2

... Pin Configurations Figure 1-1. Pinout ATmega48/88/168 TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. ...

Page 3

... As inputs, Port D pins that are externally pulled low will source current if the pull-up 2545S–AVR–07/10 “System Clock and Clock Options” on page Table 28-3 on page ATmega48/88/168 “Alternate Functions of Port B” on page 26. 306. Shorter pulses are not guaran- “Alternate Functions of Port C” on page ...

Page 4

... ADC7:6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. ATmega48/88/168 4 , even if the ADC is not used. If the ADC is used, it should be connected “ ...

Page 5

... Overview The ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 6

... ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...

Page 7

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2545S–AVR–07/10 ATmega48/88/168 7 ...

Page 8

... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATmega48/88/168 8 Block Diagram of the AVR Architecture ...

Page 9

... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48/88/168 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...

Page 10

... The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega48/88/168 ...

Page 11

... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 6-2, each register is also assigned a data memory address, mapping them ATmega48/88/168 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...

Page 12

... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. ATmega48/88/168 12 The X-, Y-, and Z-registers 15 ...

Page 13

... Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back ATmega48/88/168 SP12 SP11 SP10 SP9 SP4 SP3 ...

Page 14

... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. ATmega48/88/168 14 for details. “Interrupts” on page 55 “ ...

Page 15

... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2545S–AVR–07/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega48/88/168 15 ...

Page 16

... This section describes the different memories in the ATmega48/88/168. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48/88/168 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...

Page 17

... Figure 7-1. Figure 7-2. 2545S–AVR–07/10 Program Memory Map, ATmega48 Program Memory Application Flash Section Program Memory Map, ATmega88 and ATmega168 Program Memory Application Flash Section Boot Flash Section ATmega48/88/168 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 17 ...

Page 18

... SRAM Data Memory Figure 7-3 The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used ...

Page 19

... Figure 7-4. 7.4 EEPROM Data Memory The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 20

... I/O Memory The I/O space definition of the ATmega48/88/168 is shown in All ATmega48/88/168 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

Page 21

... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be trig- gered when writing EEPE ...

Page 22

... EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. ATmega48/88/168 22 EEPROM Mode Bits Programming ...

Page 23

... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 2545S–AVR–07/10 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega48/88/168 Table 7-2 lists the typical pro- Typ Programming Time 3 ...

Page 24

... EEPROM_write(unsigned int uiAddress, unsigned char ucData Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATmega48/88/168 24 ; 2545S–AVR–07/10 ...

Page 25

... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR MSB R/W R/W R MSB R/W R/W R MSB R/W R/W R ATmega48/88/168 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ...

Page 26

... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATmega48/88/168 26 presents the principal clock systems in the AVR and their distribution. All of the clocks 38. The clock systems are detailed below. ...

Page 27

... ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t CC ATmega48/88/168 (1) CKSEL3..0 1111 - 1000 0111 - 0110 0101 - 0100 0011 ...

Page 28

... Some initial guidelines for choosing capacitors for use with crystals are given in the manufacturer should be used. ATmega48/88/168 28 Table 8-2. The frequency of the Watchdog Oscillator is voltage “ ...

Page 29

... Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega48/88/168 XTAL2 XTAL1 GND (3) CKSEL3..1 – the CKDIV8 ...

Page 30

... The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-5. Frequency Range (MHz) Notes: ATmega48/88/168 30 Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save ...

Page 31

... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATmega48/88/168 XTAL2 XTAL1 ...

Page 32

... When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section ATmega48/88/168 32 Start-up Times for the Low Frequency Crystal Oscillator Clock Selection ...

Page 33

... Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- down and Power-save Reserved 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ensure programming mode can be entered. ATmega48/88/168 (1)(2) CKSEL3..0 0010 ), the CKDIV8 CC Additional Delay from Reset (V = 5.0V) ...

Page 34

... The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC ATmega48/88/168 34 34. To run the device on an external clock, the CKSEL Fuses must be programmed Table 8-12) ...

Page 35

... System Clock Prescaler The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...

Page 36

... These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 8-14. ATmega48/88/168 ...

Page 37

... The device is shipped with the CKDIV8 Fuse programmed. Table 8-14. CLKPS3 2545S–AVR–07/10 Clock Prescaler Select CLKPS2 CLKPS1 ATmega48/88/168 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 37 ...

Page 38

... CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk ATmega48/88/168 38 presents the different clock systems in the ATmega48/88/168, and their Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators X ...

Page 39

... Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. 2545S–AVR–07/10 1. Timer/Counter2 will only keep running in asynchronous mode, see PWM and Asynchronous Operation” on page 139 “Clock Sources” on page ATmega48/88/168 (1) , and the Watchdog to continue operating , clk , and clk , while allowing the other ...

Page 40

... Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to Comparator. ATmega48/88/168 40 “PRR – Power Reduction Register” on page “Power-Down Supply Current” on page 322 “Analog Comparator” on page 240 for examples. In all other “ ...

Page 41

... input pin can cause significant current even in active mode. Digital CC “DIDR1 – Digital Input Disable Register 1” on page 242 for details. ATmega48/88/168 “Brown-out Detection” on page 46 ) are stopped, the input buffers of the device will and “DIDR0 – Digital for details “ ...

Page 42

... Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2 ...

Page 43

... Bit 4 - Res: Reserved bit This bit is reserved in ATmega48/88/168 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...

Page 44

... Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and ATmega88, the instruction placed at the Reset Vector must be an RJMP – Relative Jump – ...

Page 45

... Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega48/88/168 DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 306. The POR is activated whenever CC 45 ...

Page 46

... Figure 10-4. External Reset During Operation 10.5 Brown-out Detection ATmega48/88/168 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...

Page 47

... Figure 10-6. Watchdog System Reset During Operation 10.7 Internal Voltage Reference ATmega48/88/168 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...

Page 48

... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 10-7. Watchdog Timer ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...

Page 49

... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 2545S–AVR–07/10 ATmega48/88/168 49 ...

Page 50

... Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. ATmega48/88/168 50 (1) r16, MCUSR r16, (0xff & ...

Page 51

... Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. See ”About Code Examples” on page 7. ATmega48/88/168 51 ...

Page 52

... Initial Value • Bit 7..4: Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

Page 53

... Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed. ATmega48/88/168 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 53 ...

Page 54

... The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 10-2 on page Table 10-2. WDP3 ATmega48/88/168 54 54. Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles (4096) cycles (8192) cycles 0 ...

Page 55

... Each Interrupt Vector occupies two instruction words in ATmega168, and one instruction word in ATmega48 and ATmega88. • ATmega48 does not have a separate Boot Loader Section. In ATmega88 and ATmega168, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR ...

Page 56

... Table 11-1. Reset and Interrupt Vectors in ATmega48 (Continued) Vector No. Program Address Source 22 0x015 ADC 23 0x016 EE READY 24 0x017 ANALOG COMP 25 0x018 TWI 26 0x019 SPM READY The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48 is: Address Labels Code ...

Page 57

... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of ATmega48/88/168 57 ...

Page 58

... ATmega48/88/168 58 Reset and Interrupt Vectors Placement in ATmega88 IVSEL Reset Address 0 0x000 1 0x000 0 Boot Reset Address 1 Boot Reset Address 1. The Boot Reset Address is shown in means unprogrammed while “0” means programmed. ...

Page 59

... RESET rjmp EXT_INT0 rjmp EXT_INT1 ... ... rjmp SPM_RDY RESET: ldi r16,high(RAMEND); Main program start ATmega48/88/168 Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...

Page 60

... ADC 23 0x002C EE READY 24 0x002E ANALOG COMP 25 0x0030 TWI 26 0x0032 SPM READY Notes: ATmega48/88/168 60 out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset External Interrupt Request 0 External Interrupt Request 1 ...

Page 61

... USART_TXC jmp ADC jmp EE_RDY jmp ANA_COMP jmp TWI jmp SPM_RDY ATmega48/88/168 (1) Interrupt Vectors Start Address 0x001 Boot Reset Address + 0x0002 0x001 Boot Reset Address + 0x0002 Table 26-6 on page 280. For the BOOTRST Fuse “1” Comments ; Reset Handler ; IRQ0 Handler ...

Page 62

... When the BOOTRST Fuse is programmed, the Boot section size set to 2 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168 is: ATmega48/88/168 62 ldi r16, high(RAMEND) ...

Page 63

... IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: This bit is not available in ATmega48. 2545S–AVR–07/10 jmp RESET ...

Page 64

... MCUCR, r17 ret C Code Example void Move_interrupts(void) { uchar temp; /* Get MCUCR*/ temp = MCUCR /* Enable change of Interrupt Vectors */ MCUCR = temp|(1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp|(1<<IVSEL); } This bit is not available in ATmega48. ATmega48/88/168 64 r16, MCUCR 2545S–AVR–07/10 ...

Page 65

... Figure 12-1. Timing of pin change interrupts 2545S–AVR–07/10 26. Low level interrupt on INT0 and INT1 is detected asynchro- 26. pin_lat pcint_in_(0) PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATmega48/88/168 “Clock Systems Figure 12-1. 0 pcint_syn pcint_setflag PCIF x clk 65 ...

Page 66

... Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask are set ...

Page 67

... Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...

Page 68

... Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 2 - PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...

Page 69

... Initial Value • Bit 7 – Res: Reserved Bit This bit is an unused bit in the ATmega48/88/168, and will always read as zero. • Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...

Page 70

... Using the I/O port as General Digital I/O is described in 71. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. ATmega48/88/168 70 and Ground as indicated in CC for a complete list of parameters. ...

Page 71

... WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 86, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega48/88/168 Figure 13-2 shows a func- PUD ...

Page 72

... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t ATmega48/88/168 72 summarizes the control signals for the pin value. Port Pin Configurations ...

Page 73

... SYNC LATCH PINxn r17 Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega48/88/168 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...

Page 74

... Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ATmega48/88/168 74 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1< ...

Page 75

... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega48/88/168 Figure 13-2 can be overridden by ...

Page 76

... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega48/88/168 76 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...

Page 77

... SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) ATmega48/88/168 Table 13- ...

Page 78

... Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source. • OC1A/PCINT1 – Port B, Bit 1 ATmega48/88/168 78 2545S–AVR–07/10 ...

Page 79

... AS2 + PCINT7 • PCINT6 • PCIE0 PCIE0 (INTRC + EXTCK) • INTRC • AS2 AS2 PCINT7 INPUT PCINT6 INPUT Oscillator/Clock Oscillator Output Input ATmega48/88/168 PB5/SCK/ PB4/MISO/ (1) PCINT5 PCINT4 SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • ...

Page 80

... PC1 PC0 The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 ATmega48/88/168 80 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses), EXTCK means that external clock is selected (by the CKSEL fuses). Overriding Signals for Alternate Functions in PB3..PB0 ...

Page 81

... PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source. • ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. 2545S–AVR–07/10 ATmega48/88/168 81 ...

Page 82

... Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega48/88/168 82 and Table 13-8 relate the alternate functions of Port C to the overriding signals Figure 13-5 on page 75. Overriding Signals for Alternate Functions in PC6..PC4 PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 RSTDISBL TWEN 1 PORTC5 • PUD ...

Page 83

... PD3 OC2B (Timer/Counter2 Output Compare Match B Output) PCINT19 (Pin Change Interrupt 19) INT0 (External Interrupt 0 Input) PD2 PCINT18 (Pin Change Interrupt 18) TXD (USART Output Pin) PD1 PCINT17 (Pin Change Interrupt 17) RXD (USART Input Pin) PD0 PCINT16 (Pin Change Interrupt 16) ATmega48/88/168 Table 13-9. 83 ...

Page 84

... PORTD0 bit. PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. Table 13-10 shown in ATmega48/88/168 84 and Table 13-11 relate the alternate functions of Port D to the overriding signals Figure 13-5 on page 75. 2545S– ...

Page 85

... OC2B ENABLE 0 OC2B 0 INT1 ENABLE + INT0 ENABLE + PCINT19 • PCIE2 PCINT18 • PCIE1 1 1 PCINT19 INPUT PCINT18 INPUT INT1 INPUT INT0 INPUT – – ATmega48/88/168 PD5/T1/OC0B/ PD4/XCK/ PCINT21 T0/PCINT20 OC0B ENABLE UMSEL OC0B XCK OUTPUT PCINT21 • PCIE2 PCINT20 • PCIE2 ...

Page 86

... PORTC – The Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.6 DDRC – The Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.7 PINC – The Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial Value ATmega48/88/168 – – – PUD R for more details about this feature ...

Page 87

... PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega48/88/168 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 PIND0 ...

Page 88

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM0 bit in enable Timer/Counter0 module. ATmega48/88/168 88 “Pinout ATmega48/88/168” on page “Register Description” on page “Minimizing Power Consumption” on page 40 Figure 14-1. For the actual 2. CPU accessible I/O Regis- 100 ...

Page 89

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ATmega48/88/168 TOVn (Int.Req.) Clock Select ...

Page 90

... Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk count operations. ATmega48/88/168 90 See “Using the Output Compare Unit” on page 117. “Timer/Counter0 and Timer/Counter1 Prescalers” on page ...

Page 91

... PWM pulses, thereby making the output glitch-free. 2545S–AVR–07/10 93. (“Modes of Operation” on page shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega48/88/168 93). TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 “Modes of 91 ...

Page 92

... Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. ATmega48/88/168 92 Figure 14-4 shows a simplified ...

Page 93

... COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See “Register Description” on page 100. Table 14-2 on page “Timer/Counter Timing Diagrams” on page ATmega48/88/168 Q 1 OCnx Pin OCnx DDR 100. For fast PWM mode, refer to Table 14-4 on page 101. 92.). Table 14 ...

Page 94

... For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for ATmega48/88/168 94 Figure ...

Page 95

... OCnx ⋅ ⋅ Figure 14-6. The TCNT0 value is in the timing diagram shown as a his ATmega48/88/168 ) OCRnx OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 OC0 95 ...

Page 96

... Figure the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. ATmega48/88/168 96 Table 14-6 on page 101). The actual OC0x value will only be visible on f OCnxPWM 14-7 ...

Page 97

... Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • OCRnx changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure 2545S–AVR–07/10 ATmega48/88/168 Table 14-7 on page 102) ...

Page 98

... Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. ATmega48/88/168 98 Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled. ...

Page 99

... OCRnx OCFnx 2545S–AVR–07/10 I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega48/88/168 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP /8) clk_I/O OCRnx + 2 BOTTOM + 1 99 ...

Page 100

... WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-2. COM0A1 Table 14-3 mode. Table 14-3. COM0A1 Note: ATmega48/88/168 100 COM0A1 COM0A0 COM0B1 R/W R/W R Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode ...

Page 101

... COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM Compare Output Mode, Fast PWM Mode COM0B0 Description 0 Normal port operation, OC0B disconnected. 1 Reserved Clear OC0B on Compare Match, set OC0B at BOTTOM, 0 (non-inverting mode) Set OC0B on Compare Match, clear OC0B at BOTTOM, 1 (inverting mode) ATmega48/88/168 (1) “Phase Correct PWM Mode” on (1) 101 ...

Page 102

... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...

Page 103

... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 2545S– ...

Page 104

... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. ATmega48/88/168 104 Clock Select Bit Description CS01 CS00 Description ...

Page 105

... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...

Page 106

... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page ATmega48/88/168 106 Table 102. ...

Page 107

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 2545S–AVR–07/10 “Pinout ATmega48/88/168” on page “Register Description” on page “PRR – Power Reduction Register” on page 43 ATmega48/88/168 Figure 15-1 ...

Page 108

... The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). ATmega48/88/168 108 Count Clear ...

Page 109

... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATmega48/88/168 (See 109 ...

Page 110

... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATmega48/88/168 110 (1) (1) 1. See ” ...

Page 111

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega48/88/168 111 ...

Page 112

... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see ATmega48/88/168 112 (1) (1) 1. See ” ...

Page 113

... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega48/88/168 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 119 ...

Page 114

... When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- ATmega48/88/168 114 DATA BUS TEMP (8-bit) ...

Page 115

... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 2545S–AVR–07/10 109. ATmega48/88/168 “Accessing 16-bit Registers” (Figure 16-1 on page 136). The edge detector is also ...

Page 116

... For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization ATmega48/88/168 116 (See “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “ ...

Page 117

... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 2545S–AVR–07/10 109. ATmega48/88/168 “Accessing 16-bit Registers” 117 ...

Page 118

... The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register performed on the next compare match. For compare output actions in the ATmega48/88/168 118 Waveform ...

Page 119

... OCR1A or ICR1, and then counter (TCNT1) is cleared. 2545S–AVR–07/10 Table 15-1 on page 129. For fast PWM mode refer to 118.) “Timer/Counter Timing Diagrams” on page Figure ATmega48/88/168 Table 15-2 on Table 15-3 on 126. 15-6. The counter value (TCNT1) 119 ...

Page 120

... PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. ATmega48/88/168 120 1 2 ...

Page 121

... The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 2545S–AVR–07/10 ( TOP log R = ---------------------------------- - FPWM log ATmega48/88/168 ) Figure 15-7. The figure OCRnx/BOTTOM Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...

Page 122

... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set ATmega48/88/168 122 Table on page f ...

Page 123

... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This 2545S–AVR–07/10 ATmega48/88/168 ( ) TOP ...

Page 124

... OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and ATmega48/88/168 124 f OCnxPCPWM 15-9). Table on page ...

Page 125

... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega48/88/168 ( ) TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...

Page 126

... Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling (clk TCNTn OCRnx OCFnx Figure 15-11 ATmega48/88/168 126 f OCnxPFCPWM Figure 15-10 clk I/O clk ...

Page 127

... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega48/88/168 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...

Page 128

... Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n ATmega48/88/168 128 clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) /8) clk_I/O TOP BOTTOM BOTTOM + 1 ...

Page 129

... COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast Compare Output Mode, Fast PWM COM1A0/COM1B0 ATmega48/88/168 – – WGM11 R R shows the COM1x1:0 bit functionality when the Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match. ...

Page 130

... Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. ATmega48/88/168 130 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. ...

Page 131

... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega48/88/168 Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A BOTTOM ICR1 ...

Page 132

... Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. ATmega48/88/168 132 Figure 15-11. ...

Page 133

... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 109. ATmega48/88/168 R/W R/W R/W R See “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...

Page 134

... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...

Page 135

... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...

Page 136

... Figure 16-1. T1/T0 Pin Sampling Tn The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. ATmega48/88/168 136 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ) ...

Page 137

... Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1 PSRSYNC Note: 2545S–AVR–07/10 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( ATmega48/88/168 (1) Clear T1 T1/T0) is shown in Figure 16-1. /2.5. clk_I/O clk T0 137 ...

Page 138

... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. ATmega48/88/168 138 7 6 ...

Page 139

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM2 bit in enable Timer/Counter2 module. Figure 17-1. 8-bit Timer/Counter Block Diagram 2545S–AVR–07/10 “Pinout ATmega48/88/168” on page “Register Description” on page 152. “Minimizing Power Consumption” on page 40 Count Clear ...

Page 140

... Prescaler” on page 17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 17-2 shows a block diagram of the counter and its surrounding environment. ATmega48/88/168 140 ). T2 See “Output Compare Unit” on page 141. Table 17-1 are also used extensively throughout the section. ...

Page 141

... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 144. shows a block diagram of the Output Compare unit. ATmega48/88/168 TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk top in the following ...

Page 142

... TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. ATmega48/88/168 142 DATA BUS OCRnx = ...

Page 143

... The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. 2545S–AVR–07/10 Waveform Generator clk I/O See “Register Description” on page 152. ATmega48/88/168 Figure 17-4 shows a simplified OCnx 0 D ...

Page 144

... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. ATmega48/88/168 144 Table 17-5 on page 153. For fast PWM mode, refer to Table 17-7 on page 143.). “ ...

Page 145

... DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. 2545S–AVR–07/ clk_I ------------------------------------------------- - OCnx ⋅ ⋅ OCRnx 1 + Flag is set in the same timer clock cycle that the TOV2 ATmega48/88/168 OCnx Interrupt Flag Set (COMnx1 OC2A ) 145 = ...

Page 146

... COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform ATmega48/88/168 146 Figure 17-6. The TCNT2 value is in the timing diagram shown as a his- ...

Page 147

... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM 2545S–AVR–07/10 17-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating 1 ATmega48/88/168 = f /2 when OCR2A is set to zero. This fea- oc2 clk_I/O ...

Page 148

... MAX value in all modes other than phase correct PWM mode. Figure 17-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 17-9 ATmega48/88/168 148 f OCnxPCPWM Figure 17-7 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn ...

Page 149

... OCF2A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 TOP ATmega48/88/168 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value BOTTOM BOTTOM + 1 TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 149 ...

Page 150

... The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. ATmega48/88/168 150 Enable interrupts, if needed. 2545S–AVR–07/10 ...

Page 151

... Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 PSRASY 2545S–AVR–07/10 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) clk I/O clk T2S Clear TOSC1 AS2 CS20 CS21 CS22 ATmega48/88/168 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 151 ...

Page 152

... When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 17-2. COM2A1 Table 17-3 on page 153 to fast PWM mode. ATmega48/88/168 152 . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S ...

Page 153

... COM2B1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected. 1 Toggle OC2B on Compare Match 0 Clear OC2B on Compare Match 1 Set OC2B on Compare Match ATmega48/88/168 (1) “Fast PWM Mode” on page 145 (1) “Phase Correct PWM Mode” on 153 ...

Page 154

... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...

Page 155

... Fast PWM Reserved PWM, Phase Correct Reserved Fast PWM 1. MAX= 0xFF 2. BOTTOM= 0x00 FOC2A FOC2B – ATmega48/88/168 Update of TOP OCRx at 0xFF Immediate 0xFF TOP OCRA Immediate 0xFF BOTTOM – – OCRA TOP – – OCRA BOTTOM – WGM22 CS22 CS21 R/W ...

Page 156

... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-9 ...

Page 157

... Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. 2545S–AVR–07/ OCR2B[7:0] R/W R/W R/W R – – – – – – – – ATmega48/88/168 R/W R/W R/W R – OCIE2B OCIE2A TOIE2 R R/W R/W R – OCF2B OCF2A TOV2 R R/W R/W R OCR2B TIMSK2 ...

Page 158

... When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. ATmega48/88/168 158 7 ...

Page 159

... TSM bit is set. Refer to the description of the chronization Mode” on page 138 2545S–AVR–07/ TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega48/88/168 – – PSRASY PSRSYNC GTCCR R R R/W R “Bit 7 – TSM: Timer/Counter Syn- 159 ...

Page 160

... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48/88/168 and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 198. The PRSPI bit in module. ...

Page 161

... Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission 2545S–AVR–07/10 (1) DIVIDER /2/4/8/16/32/64/128 1. Refer to Figure 1-1 on page 2, and ATmega48/88/168 Table 13-3 on page 77 for SPI pin placement. Figure 18-2. The sys- 161 ...

Page 162

... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB3, replace DD_MOSI with DDB3 and DDR_SPI with DDRB. ATmega48/88/168 162 Table 18-1 on page 162. For more details on automatic port overrides, refer to 75 ...

Page 163

... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See ”About Code Examples” on page 7. ATmega48/88/168 163 ...

Page 164

... DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATmega48/88/168 164 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( See ”About Code Examples” on page 7. ...

Page 165

... This is clearly seen by summarizing Table 18-3 2545S–AVR–07/10 Figure 18-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 18-4, as done below. ATmega48/88/168 Figure 165 ...

Page 166

... Table 18-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 ATmega48/88/168 166 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) SCK (CPOL = 0) mode 0 ...

Page 167

... Figure 18-3 and Figure 18-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 18-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega48/88/168 CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 18-4 for an example ...

Page 168

... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...

Page 169

... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 2545S–AVR–07/ MSB R/W R/W R/W R ATmega48/88/168 LSB R/W R/W R/W R SPDR Undefined 169 ...

Page 170

... Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATmega48/88/168 170 “Minimizing Power Consumption” on page 40 ...

Page 171

... UBRRn [H:L] BAUD RATE GENERATOR UDRn(Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDRn (Receive) UCSRnA 1. Refer to Figure 1-1 on page 2 and shows a block diagram of the clock generation logic. ATmega48/88/168 Clock Generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...

Page 172

... The baud rate generator out- put is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. ATmega48/88/168 172 UBRRn foscn ...

Page 173

... BAUD BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRnH and UBRRnL Registers, (0-4095) 194). ATmega48/88/168 Equation for Calculating (1) Rate UBRRn Value UBRRn = f ...

Page 174

... The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • data bits • no, even or odd parity bit • stop bits ATmega48/88/168 174 Figure 19-2 for details. depends on the stability of the system clock source therefore recommended to osc ...

Page 175

... No transfers on the communication line (RxDn or TxDn). An IDLE line high. ⊕ even n 1 – ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATmega48/88/168 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...

Page 176

... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. ATmega48/88/168 176 2545S–AVR–07/10 ...

Page 177

... USART_Init(MYUBRR) /*Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); 1. See ”About Code Examples” on page 7. ATmega48/88/168 177 ...

Page 178

... C Code Example void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; } Note: ATmega48/88/168 178 (1) UDRn,r16 ( See ”About Code Examples” on page 7. 2545S–AVR–07/10 ...

Page 179

... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See ”About Code Examples” on page 7. ATmega48/88/168 179 ...

Page 180

... When the first stop bit is received, that is, a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. ATmega48/88/168 180 2545S–AVR–07/10 ...

Page 181

... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See ”About Code Examples” on page 7. ATmega48/88/168 181 ...

Page 182

... Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. ATmega48/88/168 182 (1) r18, UCSRnA r17, UCSRnB r16, UDRn r17, HIGH(-1) r16, LOW(-1) ...

Page 183

... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 2545S–AVR–07/10 “Parity Bit Calculation” on page 175 ATmega48/88/168 and “Parity Checker” on page 183. 183 ...

Page 184

... Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity). ATmega48/88/168 184 (1) ...

Page 185

... RxD IDLE Sample (U2X = Sample (U2X = RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning of the start bit ATmega48/88/168 START Figure 19-6 shows the sampling of the data bits and BIT ...

Page 186

... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 19-2 that Normal Speed mode has higher toleration of baud rate variations. ATmega48/88/168 186 RxD Figure 19-7. For Double Speed mode the first low level must be delayed to ...

Page 187

... ATmega48/88/168 Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Recommended Max Max Total Error (%) Receiver Error (%) +5 ...

Page 188

... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. ATmega48/88/168 188 2545S–AVR–07/10 ...

Page 189

... The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). 2545S–AVR–07/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega48/88/168 R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA 189 ...

Page 190

... Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. ATmega48/88/168 190 “Multi-processor Communication Mode” on page ...

Page 191

... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn Bits Settings UMSELn0 See “USART in SPI Mode” on page 198 operation ATmega48/88/168 UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 19-4. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) ...

Page 192

... Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). ATmega48/88/168 192 UPMn Bits Settings UPMn0 ...

Page 193

... R/W R/W R/W R 186). The error values are calculated using the following equation: BaudRate ⎛ Closest Match Error[%] = ------------------------------------------------- - 1 ⎝ BaudRate ATmega48/88/168 Received Data Sampled (Input on RxDn Pin) Falling XCKn Edge Rising XCKn Edge UBRRn[11: R/W R/W R/W R/W R/W R/W R/W ...

Page 194

... Max. 62.5 Kbps 125 Kbps Note: 1. UBRRn = 0, Error = 0.0% ATmega48/88/168 194 f = 1.8432 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 47 0.0% 95 0.2% 23 0.0% 47 0.2% 11 0.0% 23 -3. ...

Page 195

... Kbps 0.5 Mbps ATmega48/88/168 f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...

Page 196

... Max. 0.5 Mbps 1 Mbps 1. UBRRn = 0, Error = 0.0% ATmega48/88/168 196 11.0592 f = MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn -0.1% 287 0.0% 575 0.2% 143 0.0% 287 0.2% 71 0.0% 143 0. ...

Page 197

... Mbps 2.304 Mbps ATmega48/88/168 f = 20.0000 MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.0% 520 0.0% 1041 0.0% 259 0.2% 520 0.0% 129 0.2% 259 0. ...

Page 198

... USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see ATmega48/88/168 198 Table 20-1: 2545S–AVR–07/10 ...

Page 199

... Table 20-2. Note that changing the setting of any of these bits will corrupt UCPOLn and UCPHAn Functionality- UCPHAn SPI Mode ATmega48/88/168 Equation for Calculating UBRRn (1) f OSC UBRRn ( ) + 1 Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) ...

Page 200

... Transmitter has completed all transfers, and the RXCn Flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written used for this purpose. ATmega48/88/168 200 UCPOL=0 ...

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