ATMEGA48-20MUR Atmel, ATMEGA48-20MUR Datasheet

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ATMEGA48-20MUR

Manufacturer Part Number
ATMEGA48-20MUR
Description
MCU AVR 4KB FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA48-20MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48-20MUR
Manufacturer:
Microchip Technology
Quantity:
406
Features
Note:
High Performance, Low Power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Temperature Range:
Speed Grade:
Low Power Consumption
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
– 4/8/16 Kbytes of In-System Self-programmable Flash program memory
– 256/512/512 Bytes EEPROM
– 512/1K/1K Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
– 6-channel 10-bit ADC in PDIP Package
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– DebugWIRE On-Chip Debug System
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
– 1.8V - 5.5V for ATmega48V/88V/168V
– 2.7V - 5.5V for ATmega48/88/168
– -40
– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V
– ATmega48/88/168: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V
– Active Mode:
– Power-down Mode:
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
250 µA at 1 MHz, 1.8V
15 µA at 32 kHz, 1.8V (including Oscillator)
0.1 µA at 1.8V
1. See
°
C to 85
“Data Retention” on page 7
°
C
®
AVR
for details.
®
8-Bit Microcontroller
2
C compatible)
()
8-bit
Microcontroller
with 4/8/16K
Bytes In-System
Programmable
Flash
ATmega48/V
ATmega88/V
ATmega168/V
Summary
Rev. 2545SS–AVR–07/10

Related parts for ATMEGA48-20MUR

ATMEGA48-20MUR Summary of contents

Page 1

... • Speed Grade: – ATmega48V/88V/168V MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega48/88/168 MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Low Power Consumption – Active Mode: 250 µ MHz, 1.8V 15 µ kHz, 1.8V (including Oscillator) – Power-down Mode: 0.1 µA at 1.8V Note: 1 ...

Page 2

... Pin Configurations Figure 1-1. Pinout ATmega48/88/1682545SS TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. ...

Page 3

... Reset. The various special features of Port C are elaborated in 80. 2545SS–AVR–07/10 “System Clock and Clock Options” on page Table 26-3 on page ATmega48/88/168 “Alternate Functions of Port B” on page 26. 306. Shorter pulses are not guaran- “Alternate Functions of Port C” on page 3 ...

Page 4

... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 2545SS–AVR–07/10 , even if the ADC is not used. If the ADC is used, it should be connected ATmega48/88/168 “Alternate Functions of Port D” on page . CC CC ...

Page 5

... Overview The ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 6

... ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...

Page 7

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 2545SS–AVR–07/10 ATmega48/88/168 7 ...

Page 8

... USART I/O Data Register USART Baud Rate Register Low – – – UMSEL00 UPM01 UPM00 USBS0 TXCIE0 UDRIE0 RXEN0 TXEN0 TXC0 UDRE0 FE0 DOR0 ATmega48/88/168 Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – – ...

Page 9

... FOC1B – – ICES1 – WGM13 WGM12 COM1A0 COM1B1 COM1B0 – – – – ADC5D ADC4D ADC3D ATmega48/88/168 Bit 2 Bit 1 Bit 0 – – – – – – – – TWAM1 TWAM0 – TWEN – TWIE TWA1 TWA0 TWGCE – ...

Page 10

... Address Register High Byte) EEPROM Address Register Low Byte EEPROM Data Register – EEPM1 EEPM0 General Purpose I/O Register 0 – – – – – – ATmega48/88/168 Bit 3 Bit 2 Bit 1 Bit 0 – – – – MUX3 MUX2 MUX1 MUX0 – ...

Page 11

... When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions ...

Page 12

... PC ← then PC ← then PC ← then PC ← then PC ← ⊕ then PC ← ⊕ then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATmega48/88/168 Operation Flags #Clocks Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V ...

Page 13

... Y ← (Y) ← ← Rr (Z) ← Rr (Z) ← Rr, Z ← ← (Z) ← ← Rr (k) ← ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← ← Rr STACK ← Rr ATmega48/88/168 Operation Flags #Clocks None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None ...

Page 14

... Watchdog Reset BREAK Break Note: 1. These instructions are only available in ATmega168. 2545SS–AVR–07/10 Description Rd ← STACK (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only ATmega48/88/168 Operation Flags #Clocks None None None None None 2 1 ...

Page 15

... Wide, Plastic Dual Inline Package (PDIP) 2545SS–AVR–07/10 Ordering Code ATmega48V-10AI ATmega48V-10MI ATmega48V-10PI (2) ATmega48V-10AU (2) ATmega48V-10MMU (2) ATmega48V-10MU (2) ATmega48V-10PU ATmega48-20AI ATmega48-20MI ATmega48-20PI (2) ATmega48-20AU (2) ATmega48-20MMU (2) ATmega48-20MU (2) ATmega48-20PU and Figure 26-2 on page 304. Package Type ATmega48/88/168 (1) Package Operational Range 32A 32M1-A 28P3 ...

Page 16

... Ordering Code ATmega88V-10AI ATmega88V-10MI ATmega88V-10PI (2) ATmega88V-10AU (2) ATmega88V-10MU (2) ATmega88V-10PU ATmega88-20AI ATmega88-20MI ATmega88-20PI (2) ATmega88-20AU (2) ATmega88-20MU (2) ATmega88-20PU and Figure 26-2 on page 304. Package Type ATmega48/88/168 (1) Package Operational Range 32A 32M1-A 28P3 Industrial ° 32A (- 32M1-A 28P3 32A 32M1-A 28P3 Industrial ° 32A (- 32M1-A 28P3 ° ...

Page 17

... Ordering Code ATmega168V-10AI ATmega168V-10MI ATmega168V-10PI (2) ATmega168V-10AU (2) ATmega168V-10MU (2) ATmega168V-10PU ATmega168-20AI ATmega168-20MI ATmega168-20PI (2) ATmega168-20AU (2) ATmega168-20MU (2) ATmega168-20PU and Figure 26-2 on page 304. Package Type ATmega48/88/168 (1) Package Operational Range 32A 32M1-A 28P3 Industrial ° 32A (- 32M1-A 28P3 32A 32M1-A 28P3 Industrial ° 32A (- 32M1-A 28P3 ° ...

Page 18

... Orchard Parkway San Jose, CA 95131 R 2545SS–AVR–07/10 B PIN 1 IDENTIFIER TITLE 32A, 32-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega48/88/168 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A – – 1.20 A1 0.05 – ...

Page 19

... Package Drawing Contact: packagedrawings@atmel.com 2545SS–AVR–07/ TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ATmega48/88/168 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX A 0.80 0.90 1 ...

Page 20

... San Jose, CA 95131 R 2545SS–AVR–07/ TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega48/88/168 SIDE VIEW A3 A1 COMMON DIMENSIONS 0.08 C (Unit of Measure = mm) MIN NOM MAX SYMBOL A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – ...

Page 21

... Orchard Parkway San Jose, CA 95131 R 2545SS–AVR–07/10 D PIN PLACES 0º ~ 15º REF eB TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) ATmega48/88/168 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX A – – 4.5724 A1 0.508 – D 34.544 – ...

Page 22

... Errata 8.1 Errata ATmega48 The revision letter in this section refers to the revision of the ATmega48 device. 8.1.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00 ...

Page 23

... necessary to read an EEPROM location after Erase Only, use an Atomic Write opera- tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased loca- tion is not read before it is programmed. 2545SS–AVR–07/10 ATmega48/88/168 23 ...

Page 24

... Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 2545SS–AVR–07/10 ATmega48/88/168 24 ...

Page 25

... A reset is applied window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. 2545SS–AVR–07/10 ATmega48/88/168 25 ...

Page 26

... System Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: - Two succeeding resets are applied where the second reset occurs in the 10 ns window before the device is out of the reset-state caused by the first reset. 2545SS–AVR–07/10 ATmega48/88/168 26 ...

Page 27

... The problem is most often seen during In- System Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: 2545SS–AVR–07/10 ATmega48/88/168 27 ...

Page 28

... Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 2545SS–AVR–07/10 ATmega48/88/168 28 ...

Page 29

... Merged the sections Resources, Data Retention and About Code Examples under one common section, “Resources” on page Updated Figure 8-4 on page 34. Updated “System Clock Prescaler” on page ATmega48/88/168 349. Table 28-3 on page 306. “System and Reset Characteristics” on and added the note “Not recommended for new 7. 35. ...

Page 30

... MCU Control Register” on page Updated “System and Reset Characteristics” on page Updated Note in Table 8-3 on page Table 8-10 on page 33. Updated “Interrupts” on page 55. Updated“Errata ATmega48” on page 357 Changed description in “Analog-to-Digital Converter” on page Updated “Features” on page 1. Updated Table 1-1 on page 2. Updated “ ...

Page 31

... Added Table 28-1 on page 305. Updated Figure 15-7 on page 121, Updated rev “Errata ATmega48” on page Added rev. C and D in “Errata ATmega48” on page Added Section 3. “Resources” on page 7 Update Section 8.6 “Calibrated Internal RC Oscillator” on page ATmega48/88/168 46 ...

Page 32

... Updated equation in “Bit Rate Generator Unit” on page Speed Grades changed: 12MHz to 10MHz and 24MHz to 20MHz Updated “Speed Grades” on page Updated “Ordering Information” on page Updated “Errata ATmega88” on page ATmega48/88/168 updated. 357. 21. 32. 34. Table 28-6 on page 308, Table 28-2 on page 89 ...

Page 33

... Table 23-1 on page 284. Fixed typo in Table 12-1 on page Updated whole “Typical Characteristics” on page Added item “Errata ATmega48” on page Renamed the following bits: - SPMEN to SELFPRGEN - PSR2 to PSRASY - PSR10 to PSRSYNC - Watchdog Reset to Watchdog System Reset Updated C code examples containing old IAR syntax. ...

Page 34

...

Page 35

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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