AT89C4051-24PU Atmel, AT89C4051-24PU Datasheet - Page 6

• Manufacturer Part Number: AT89C4051-24PU
• Description: IC MCU 4K FLASH 24MHZ 20-DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C4051-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP W
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

7. Restrictions on Certain Instructions
7.1
7.2
8. Program Memory Lock Bits
6
Branching Instructions
MOVX-related Instructions, Data Memory
AT89C4051
The AT89C4051 is an economical and cost-effective member of Atmel’s growing family of micro-
controllers. It contains 4K bytes of Flash program memory. It is fully compatible with the MCS-51
architecture, and can be programmed using the MCS-51 instruction set. However, there are a
few considerations one must keep in mind when utilizing certain instructions to program this
device.
All the instructions related to jumping or branching should be restricted such that the destination
address falls within the physical program memory space of the device, which is 4K for the
AT89C4051. This should be the responsibility of the software programmer. For example, LJMP
0FE0H would be a valid instruction for the AT89C4051 (with 4K of memory), whereas LJMP
1000H would not.
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching instruc-
tions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (loca-
tions 00H to FFFH for the 89C4051). Violating the physical space limits may cause unknown
program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ. With these conditional branching
instructions the same rule above applies. Again, violating the memory boundaries may cause
erratic execution.
For applications involving interrupts, the normal interrupt service routine address locations of the
80C51 family architecture have been preserved.
The AT89C4051 contains 128 bytes of internal data memory. Thus, in the AT89C4051 the stack
depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is
not supported in this device, nor is external Program memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the controller user to know the physi-
cal features and limitations of the device being used and adjust the instructions used
correspondingly.
On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to
obtain the additional features listed in the
Table 8-1.
Note:
1
2
3
1. The Lock Bits can only be erased with the Chip Erase operation.
Program Lock Bits
Lock Bit Protection Modes
LB1
U
P
P
LB2
U
U
P
(1)
Table
Protection Type
No program lock features
Further programming of the Flash is disabled
Same as mode 2, also verify is disabled
8-1.
1001F–MICRO–6/08