AT89C4051-24PU Atmel, AT89C4051-24PU Datasheet - Page 7

• Manufacturer Part Number: AT89C4051-24PU
• Description: IC MCU 4K FLASH 24MHZ 20-DIP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C4051-24PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Cpu Family: 89C
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 24MHz
• Interface Type: UART
• Total Internal Ram Size: 128Byte
• # I/os (max): 15
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 20
• Package Type: PDIP W
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

9. Idle Mode
10. Power-down Mode
11. Brown-out Detection
1001F–MICRO–6/08
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.
In the power-down mode the oscillator is stopped and the instruction that invokes power-down is
the last instruction executed. The on-chip RAM and Special Function Registers retain their val-
ues until the power-down mode is terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be
activated before V
enough to allow the oscillator to restart and stabilize.
P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external
pullups are used.
When V
pulled high. When V
delay of typically 15 msec. The nominal brown-out detection threshold is 2.1V ± 10%.
CC
INTERNAL RESET
drops below the detection threshold, all port pins (except P1.0 and P1.1) are weakly
PORT PIN
CC
CC
is restored to its normal operating level and must be held active long
goes back up again, an internal Reset is automatically generated after a
V
CC
2.1V
2.1V
15 msec.
AT89C4051
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