ATTINY43U-SUR Atmel, ATTINY43U-SUR Datasheet - Page 101
ATTINY43U-SUR
Manufacturer Part Number
ATTINY43U-SUR
Description
MCU AVR 4KB FLASH 8MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY43U-SU.pdf
(182 pages)
Specifications of ATTINY43U-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.3
14.3.1
8048B–AVR–03/09
Functional Descriptions
Three-wire Mode
output to the opposite clock edge of the data input sampling. The serial input is always sampled
from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and it can generate an overflow
interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same
clock source. This allows the counter to count the number of bits received or transmitted and
generate an interrupt when the transfer is complete. Note that when an external clock source is
selected the counter counts both clock edges. This means the counter registers the number of
clock edges and not the number of data bits. The clock can be selected from three different
sources: The USCK pin, Timer/Counter0 Compare Match or from software.
The two-wire clock control unit can be configured to generate an interrupt when a start condition
has been detected on the two-wire bus. It can also be set to generate wait states by holding the
clock pin low after a start condition is detected, or after the counter overflows.
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 14-2. Three-wire Mode Operation, Simplified Diagram
Figure 14-2
The two USI Data Registers are interconnected in such way that after eight USCK clocks, the
data in each register has been interchanged. The same clock also increments the USI’s 4-bit
counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine
when a transfer is completed. The clock is generated by the Master device software by toggling
the USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR.
SLAVE
MASTER
Bit7
Bit7
shows two USI units operating in three-wire mode, one as Master and one as Slave.
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
PORTxn
USCK
USCK
DO
DO
DI
DI
101
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