ATTINY43U-SUR Atmel, ATTINY43U-SUR Datasheet - Page 61
ATTINY43U-SUR
Manufacturer Part Number
ATTINY43U-SUR
Description
MCU AVR 4KB FLASH 8MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY43U-SU.pdf
(182 pages)
Specifications of ATTINY43U-SUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.3.4
10.3.5
8048B–AVR–03/09
PCMSK1 – Pin Change Mask Register 1
PCMSK0 – Pin Change Mask Register 0
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bits 7:0 – PCINT[15:8]: Pin Change Enable Mask 15:8
Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin, or not. If PCINT15:8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corre-
sponding I/O pin is disabled.
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the cor-
responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
Bit
0x20 (0x40)
Read/Write
Initial Value
Bit
0x12 (0x32)
Read/Write
Initial Value
PCINT15
PCINT7
R/W
7
0
R
7
0
PCINT14
PCINT6
R/W
R/W
6
0
6
0
PCINT13
PCINT5
R/W
R/W
5
0
5
0
PCINT12
PCINT4
R/W
R/W
4
0
4
0
PCINT11
PCINT3
R/W
R/W
3
0
3
0
PCINT10
PCINT2
R/W
R/W
2
0
2
0
PCINT9
PCINT1
R/W
R/W
1
0
1
0
PCINT8
PCINT0
R/W
R/W
0
0
0
0
PCMSK1
PCMSK0
61
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