ATMEGA48PA-MMH Atmel, ATMEGA48PA-MMH Datasheet - Page 250

• Manufacturer Part Number: ATMEGA48PA-MMH
• Description: MCU AVR 4KB FLASH IND 28QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA48PA-MMH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: ATMEGA48x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, TWI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.3
8271C–AVR–08/10
DIDR1 – Digital Input Disable Register 1
• Bit 7:2 – Reserved
These bits are unused bits in the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P, and will
always read as zero.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
(0x7F)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
2
–
R
0
AIN1D
R/W
1
0
AIN0D
R/W
0
0
DIDR1
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