ATMEGA48P-20AUR Atmel, ATMEGA48P-20AUR Datasheet - Page 213
![MCU AVR 4K FLASH 20MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA48P-20AUR
Manufacturer Part Number
ATMEGA48P-20AUR
Description
MCU AVR 4K FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA168P-20AU.pdf
(420 pages)
Specifications of ATMEGA48P-20AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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21.2.1
21.2.2
8025L–AVR–7/10
TWI Terminology
Electrical Interconnection
The following definitions are frequently encountered in this section.
Table 21-1.
The PRTWI bit in
the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
Term
Master
Slave
Transmitter
Receiver
TWI Terminology
Figure
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
”Minimizing Power Consumption” on page 43
21-1, both bus lines are connected to the positive supply voltage through
”2-wire Serial Interface Characteristics” on page
ATmega48P/88P/168P
must be written to zero to enable
317. Two
213
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