PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 117

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.2.5
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit erased (PWRT disabled), there will be
no time-out at all. Figure 11.2.1, Figure 11-5 and
Figure 11-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.7.2 “Two-Speed Start-up Sequence” and
Section 3.8 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 11-5). This is useful for testing purposes or
to synchronize more than one PIC16F688 device
operating in parallel.
Table 11-5 shows the Reset conditions for some
special registers, while Table 11-4 shows the Reset
conditions for all the registers.
TABLE 11-1:
TABLE 11-2:
TABLE 11-3:
© 2009 Microchip Technology Inc.
CONFIG
PCON
STATUS
Legend:
Note
XT, HS, LP
RC, EC, INTOSC
Legend: u = unchanged, x = unknown
Oscillator Configuration
Name
POR
0
1
u
u
u
u
1:
2:
(2)
BOREN1 BOREN0
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 11-1) for operation of all register bits.
TIME-OUT SEQUENCE
Bit 9
BOR
u
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 8
TO
1
1
0
0
u
1
Bit 7
CPD
IRP
—
T
PWRTE = 0
PWRT
• T
T
PD
PWRT
1
1
u
0
u
0
OSC
Bit 6
RP1
CP
+ 1024
—
Power-up
ULPWUE SBOREN
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
MCLRE
Bit 5
RP0
PWRTE = 1
1024 • T
PWRTE
—
Bit 4
TO
OSC
11.2.6
The Power Control (PCON) register (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0>
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.4 “Ultra
Low-Power
“Brown-Out Reset (BOR)”.
WDTE
Bit 3
PD
—
T
PWRTE = 0
PWRT
FOSC2
• T
T
Bit 2
PWRT
—
Z
OSC
Brown-out Reset
+ 1024
POWER CONTROL (PCON)
REGISTER
Condition
FOSC1
Bit 1
POR
Wake-up”
DC
= 00 in the Configuration Word
PWRTE = 1
1024 • T
FOSC0
Bit 0
BOR
C
PIC16F688
—
OSC
--01 --qq
0001 1xxx
and
POR, BOR
Value on
—
DS41203E-page 115
Section 11.2.4
1024 • T
DD
from Sleep
Wake-up
--0u --uu
000q quuu
may have
Value on
Resets
—
all other
—
OSC
(1)