PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 34

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
FIGURE 3-9:
TABLE 3-2:
DS41203E-page 32
CONFIG
INTCON
OSCCON
OSCTUNE
PIE1
PIR1
Legend:
Note 1:
Clock Monitor Output
Name
2:
Sample Clock
(2)
Note:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (CONFIG) for operation of all register bits.
OSCFIF
System
Output
Clock
EEIE
EEIF
Bit 7
CPD
GIE
—
—
(Q)
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
IRCF2
PEIE
ADIE
ADIF
Bit 6
CP
—
MCLRE
IRCF1
RCIE
RCIF
Bit 5
T0IE
—
Test
PWRTE
IRCF0
TUN4
Bit 4
INTE
C2IE
C2IF
WDTE
OSTS
TUN3
RAIE
Bit 3
C1IE
C1IF
FOSC2
OSFIE
OSFIF
TUN2
Bit 2
T0IF
HTS
Test
Oscillator
Failure
FOSC1
TUN1
Bit 1
INTF
TXIE
TXIF
LTS
TMR1IE
TMR1IF
FOSC0
TUN0
RAIF
Bit 0
SCS
© 2009 Microchip Technology Inc.
Detected
0000 000x
-110 x000
---0 0000
0000 0000
0000 0000
POR, BOR
Value on
Failure
—
Test
0000 000x
-110 x000
---u uuuu
0000 0000
0000 0000
Resets
Value on
all other
—
(1)