PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 40

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
4.2.4.5
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 4-5:
DS41203B-page 38
Data Bus
TRISA
PORTA
PORTA
WPUA
WPUA
TRISA
IOCA
IOCA
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
WR
WR
WR
WR
RD
RD
RD
RD
Interrupt-on-
change
2: With CLKOUT option.
3: Analog Input mode is ANSEL.
Enable.
D
D
D
D
To T1G
To A/D Converter
CK
CK
CK
CK
RA4/AN3/T1G/OSC2/CLKOUT
Q
Q
Q
Q
Q
Q
Q
Q
Input Mode
BLOCK DIAGRAM OF RA4
Analog
OSC1
Fosc/4
INTOSC/
RC/EC
CLKOUT
CLKOUT
Enable
(3)
Enable
Input Mode
RD PORTA
RAPU
Analog
CLKOUT
Enable
Oscillator
Circuit
Modes
Q
Q
1
0
(2)
CLK
(3)
EN
EN
(1)
D
D
V
DD
Weak
V
V
Q3
DD
SS
I/O pin
Preliminary
4.2.4.6
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6:
Data Bus
PORTA
PORTA
WPUA
WPUA
TRISA
TRISA
IOCA
IOCA
WR
WR
WR
WR
RD
RD
RD
RD
Interrupt-on-
change
Note
D
D
D
D
To TMR1 or CLKGEN
CK
CK
CK
CK
1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the
RA5/T1CKI/OSC1/CLKIN
Schmitt Trigger is bypassed.
Q
Q
Q
Q
Q
Q
Q
Q
BLOCK DIAGRAM OF RA5
INTOSC
 2004 Microchip Technology Inc.
OSC2
Mode
INTOSC
RD PORTA
RAPU
Mode
Oscillator
Circuit
TMR1LPEN
Q
Q
EN
EN
D
D
V
(1)
DD
Weak
V
V
DD
Q3
SS
I/O pin
(2)