PIC16F688-I/P Microchip Technology, PIC16F688-I/P Datasheet - Page 86

• Manufacturer Part Number: PIC16F688-I/P
• Description: IC PIC MCU FLASH 4KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 3.3 mm
• Length: 19.05 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC162061 - HEADER INTRFC MPLAB ICD2 20PINDM163029 - BOARD PICDEM FOR MECHATRONICSAC162056 - HEADER INTERFACE ICD2 16F688ACICE0207 - MPLABICE 14P 300 MIL ADAPTERAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F688
TABLE 10-3:
10.2.2
The EUSART module supports the automatic detection
and calibration of baud rate. This feature is active only
in Asynchronous mode and while the WUE bit is clear.
The automatic baud rate measurement sequence
(Figure 10-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is self-
averaging.
In the Auto Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal baud rate generator is used as
a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto Baud Detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus sync character), in order to
calculate the proper bit rate. The measurement takes
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the pre-configured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes, by checking for 00h in
the SPBRGH register. Refer to Table 10-4 for counter
clock rates to the BRG.
DS41203B-page 84
BAUD
RATE
115.2
19.2
57.6
(K)
0.3
1.2
2.4
9.6
111.111
Actual
19.231
58.824
0.300
1.200
2.404
9.615
Rate
AUTO BAUD RATE DETECT
(K)
F
OSC
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
= 4.000 MHz
Error
-3.55
0.01
0.04
0.16
0.16
0.16
2.12
%
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
(decimal)
SPBRG
value
3332
832
415
103
51
16
8
Actual
19230
55555
Rate
1201
2403
9615
300
(K)
—
F
OSC
= 2.000 MHz
Error
-0.04
-0.16
-0.16
-0.16
-0.16
3.55
—
%
Preliminary
(decimal)
SPBRG
value
1665
415
207
51
25
—
8
While the ABD sequence takes place, the USART state
machine is held in IDLE. The RCIF interrupt is set once
the fifth rising edge on RX is detected. The value in the
RCREG needs to be read to clear the RCIF interrupt.
RCREG content should be discarded.
TABLE 10-4:
BRG16
Actual
19230
Note:
Rate
1201
2403
9615
Note 1: If the WUE bit is set with the ABDEN bit,
300
(K)
—
—
0
0
1
1
F
OSC
2: It is up to the user to determine that the
= 1.000 MHz
BRGH
Error
-0.04
-0.16
-0.16
-0.16
-0.16
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit
counter, independent of BRG16 setting.
auto baud rate detection will occur on the
byte following the Break character (see
Section 10.3.4
SYNC Break Character”).
incoming character baud rate is within the
range of the selected BRG clock source.
Some
frequency and USART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the Auto Baud Rate Detection
feature.
—
—
%
0
1
0
1
BRG COUNTER CLOCK
RATES
(decimal)
SPBRG
value
832
207
103
25
12
—
—
combinations
 2004 Microchip Technology Inc.
BRG Counter Clock
“Auto-Wake-up
F
F
F
F
OSC
OSC
OSC
OSC
/512
/128
/128
/32
of
oscillator
on