ATMEGA8U2-MU Atmel, ATMEGA8U2-MU Datasheet - Page 57
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ATMEGA8U2-MU
Manufacturer Part Number
ATMEGA8U2-MU
Description
MCU AVR 8K FLASH USB 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Package
32QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 57 of 309
- Download datasheet (6Mb)
10.5.3
7799D–AVR–11/10
WDTCKD – Watchdog Timer Clock Divider Register
function of the Watchdog System Reset mode. If the interrupt is not executed before the next
time-out, a System Reset will be applied.
Table 10-1.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table on page
• Bit 7:6 - Res: Reserved bits
These bits are reserved and will always read as zero.
• Bit 5 - WDEWIFCL: Watchdog Early Warning Flag Clear Mode
When this bit has been set by software, the WDEWIF interrupt flag is not cleared by hardware
when entering the Watchdog Interrupt subroutine (it has to be cleared by software by writing a
logic one to the flag).
When cleared, the WDEWIF is cleared by hardware when executing the corresponding interrupt
handling vector.
• Bit 4 - WCLKD2 bit: Watchdog Timer Clock Divider
See
Bit
(0x62)
Read/Write
Initial Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
WDTON (Fuse)
“Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider” on page
Watchdog Timer Configuration
R
7
0
-
58.
R
6
0
-
WDE
0
0
1
1
x
WIFCM
WDE-
R/W
5
0
WDIE
0
1
0
1
x
WCLKD2
R/W
4
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System
Reset Mode
System Reset Mode
WDEWIF
R/W
ATmega8U2/16U2/32U2
3
0
WDEWIE
R/W
2
0
WCLKD1
58.
R/W
1
0
Action on 2x Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
WCLKD0
R/W
0
0
WDTCKD
57
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