ATMEGA8515L-8MUR Atmel, ATMEGA8515L-8MUR Datasheet - Page 114
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ATMEGA8515L-8MUR
Manufacturer Part Number
ATMEGA8515L-8MUR
Description
MCU AVR 8KB FLASH 8MHZ 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8515L-8MC.pdf
(257 pages)
Specifications of ATMEGA8515L-8MUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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ATmega8515(L)
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-
TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or
ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are
updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-
erate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the compare registers. If the TOP value is lower
than any of the compare registers, a Compare Match will never occur between the
TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are
masked to zero when any of the OCR1x Registers are written. As the third period shown
in Figure 54 illustrates, changing the TOP actively while the Timer/Counter is running in
the phase correct mode can result in an unsymmetrical output. The reason for this can
be found in the time of update of the OCR1x Register. Since the OCR1x update occurs
at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-
ing slope is determined by the previous TOP value, while the length of the rising slope is
determined by the new TOP value. When these two values differ the two slopes of the
period will differ in length. The difference in length gives the unsymmetrical result on the
output.
It is recommended to use the phase and frequency correct mode instead of the phase
correct mode when changing the TOP value while the Timer/Counter is running. When
using a static TOP value there are practically no differences between the two modes of
operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on
the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to 3 (See Table 52 on
page 120). The actual OC1x value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-
ting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x Register at Compare
Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values. If OCR1A is used to define the TOP value (WGM1 = 11) and
COM1A1:0 = 1, the OC1A Output will toggle with a 50% duty cycle.
f
OCnxPCPWM
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
2512K–AVR–01/10
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